Stack/trench diode for use with a muti-state material in a non-volatile memory cell

• US 5,841,150 A
• Filed: 02/12/1997
• Issued: 11/24/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Turi, Ray, Gonzalez, Fernando
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/799,515
• Time in Patent Office: 650 Days
• Field of Search: 257/395, 257/396, 257/397, 257/2, 257/3, 257/4, 257/5, 365/163
• US Class Current: 257/3
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The invention provides a vertically oriented diode for use in delivering large amounts of current to a variable resistance element in a multi-state memory cell. The vertical diode is disposed in a diode container extending downwardly from the top of a tall oxide stack into a deep trench in single crystal silicon. The diode is formed of a combination of single crystal and/or polycrystalline silicon layers disposed vertically inside the diode container. The memory element is formed above the diode to complete a memory cell. The vertical construction of the diode provides a large diode surface area capable of generating a very large current flow through the memory element, as is required for programming. In this way, a highly effective diode can be created for delivering a large current without requiring the substrate surface space normally associated with such large diodes.

Claims

1. A chalcogenide-based memory cell having a first node and a second node, said cell comprising:

a silicon base;

an oxide layer disposed above said silicon base;

a diode container extending from a top surface of said oxide layer downwardly into a trench formed in said silicon base, said first node being disposed in electrical communication with a perimeter of said container;

a diode disposed inside said container; and

a chalcogenide memory element electrically coupled between said diode and said second node of said memory cell.

2. The memory cell of claim 1, wherein said first node is disposed in said silicon base along said perimeter of said diode container.

3. The memory cell of claim 1, wherein a container lining is disposed along said perimeter of said container between said perimeter and said diode, said lining effective to reduce the resistance presented by said diode during operation of said cell.

4. The memory cell of claim 1, wherein said diode comprises a first silicon layer disposed around said perimeter of said container, and a second silicon layer disposed concentrically inside said first silicon layer.

5. The memory cell of claim 4, wherein said first silicon layer is an epitaxial silicon layer and wherein said second silicon layer is a polysilicon layer.

6. The memory cell of claim 1, wherein said memory cell further comprises a spacer disposed at an edge of said diode, said edge being formed where said diode emerges from said container, said spacer effective to electrically isolate said diode from surrounding regions.

7. The memory cell of claim 1, wherein said memory element comprises a chalcogenide layer and a shaping layer, said shaping layer contouring said chalcogenide layer to at least partially define a chalcogenide active area at a center of said memory cell where said chalcogenide layer is in electrical communication with said diode.

8. A chalcogenide-based memory matrix formed on a structure having an oxide layer disposed above a silicon base, said matrix comprising:

a plurality of memory cells disposed between a plurality of first address lines and second address lines, each said memory cell comprising;

(i) a first node and a second node, said first node being electrically connected to one of said first address lines and said second node being electrically connected to one of said second address lines;

(ii) a chalcogenide memory element electrically coupled to said second node; and

(iii) a diode disposed in a container extending from a top surface of said oxide layer downwardly into a trench formed in said silicon base, said diode being electrically coupled between said memory element and said first node.

9. The memory of claim 8, wherein said first node of each said memory cell is in communication with said container so as to create an electrical contact between said first node and said diode.

10. The memory of claim 9, wherein said diode of each said memory cell comprises a first silicon layer disposed about a wall of said container, and a second silicon layer disposed concentrically inside said first silicon layer.

11. The memory of claim 10, wherein said first silicon layer is a layer of P- epitaxial silicon, and wherein said second silicon layer is a layer of N+ polycrystalline silicon.

12. The memory cell of claim 9, wherein said first address line is a digitline and said second address line is a wordline.

13. The memory of claim 9, wherein said first node of each said memory cell is disposed along an upper surface of said silicon base, and wherein each said first node is a part of one of said first address lines.

14. The memory cell of claim 13, wherein a strapping layer is disposed in electrical contact with each of said first address lines across its entire length.

15. The memory of claim 14, wherein said strapping layer is a tungsten layer.

16. The memory of claim 8, wherein said silicon base is an n-well formed in a p-type substrate.