High density multi-layered printed wiring board, multi-chip carrier and semiconductor package

• US 5,841,190 A
• Filed: 02/23/1996
• Issued: 11/24/1998
• Est. Priority Date: 05/19/1995
• Status: Expired due to Term

• Current Assignee: Ibiden Co., Ltd.
• Original Assignee: Ibiden Co., Ltd.
• Inventors: Inoue, Tooru, Noda, Kouta, Yuan, Benzhen
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/601,046
• Time in Patent Office: 1,005 Days
• Field of Search: 257/697, 257/693, 257/691, 257/698, 257/700-703, 257/680, 257/678, 257/668
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/142 : Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

A semiconductor package (11) includes a high density multi-layered printed wiring board (12), a plurality of LSI chips (14,15) and a substrate supporter (13). A substrate (16) is made of a material having higher heat conductivity than that of resins. A build-up layer (17) having interlayer insulations (I1-I4) and conductive layers (C1-C5) is formed on a first side (S1) of the substrate (16). A die area (19) for mounting the LSI chips (14,15) is provided on the build-up layer (17). A plurality of I/O pads (21) are provided around the die area. The I/O pads (21) are connected to bonding pads (28) on the supporter (13) via bonding wires. The supporter (13) includes a printed wiring board (23) consisting essentially of a resin material. The wiring board (12) is fitted in a window (24) formed in the printed wiring board (23) while a second side (S2) of the substrate, which is opposite to the first side, is exposed from the window. Heat generated in the LSI chips (14,15) is efficiently released from the second side of the substrate (S2).

Claims

1. A multi-chip carrier assembly comprising:

a high density multi-layered printed wiring board including;

a substrate made of a material having a higher heat conductivity than that of resins;

a build-up layer formed on a first side of said substrate, said build-up layer being provided with interlayer insulations and conductive layers that are alternately laminated;

an electronic parts mounting area defined on a top surface of said build-up layer; and

a first plurality of I/O terminals provided, on the top surface of said build-up layer, at an area between said electronic parts mounting area and an edge of said substrate; and

a substrate supporter including;

a printed wiring board part consisting essentially of a resin material;

a window formed in said printed wiring board part and dimensioned for receipt of said high density multi-layered printed wiring board while a second side of said substrate, which is opposite to the first side of said substrate, is exposed from the window;

a plurality of bonding pads surrounding the window;

a second plurality of I/O terminals surrounding the group of said plurality of bonding pads; and

at least one conductive pattern for electrically connecting respective bonding pads and respective I/O terminals of said first plurality of I/O terminals.

2. A multi-chip carrier assembly according to claim 1, wherein each of said interlayer insulations is made of a photosensitive epoxy resin.

3. A multi-chip carrier assembly according to claim 1, wherein each of said conductive layers consists of a copper conductive layer and a groundwork layer placed between the copper conductive layer and one of said interlayer insulations, and wherein said groundwork layer includes a metal thin layer made of a metal selected from the group consisting of chrome, titanium and nickel.

4. A multi-chip carrier assembly according to claim 1, wherein each of said conductive layers has a copper conductive layer;

wherein a metal cover layer is provided between a top surface of each copper conductive layer and a bottom surface of the interlayer insulation covering the copper conductive layer; and

wherein said metal cover layer is made of a metal which improves adhesion between a copper conductive layer and an interlayer insulation associated with the copper conductive layer.

5. A multi-chip carrier assembly according to claim 4, wherein said cover layer is made of nickel.

6. A semiconductor package comprising:

a high density multi-layered printed wiring board including;

a substrate made of a material having a higher heat conductivity than that of resins;

a build-up layer formed on a first side of said substrate, said build-up layer being provided with interlayer insulations and conductive layers that are alternately laminated;

an electronic parts mounting area defined on a top surface of said build-up layer; and

a first plurality of I/O terminals provided, on the top surface of said build-up layer, at an area between said electronic parts mounting area and an edge of said substrate;

a plurality of electronic parts mounted on the electronic parts mounting area provided on said build-up layer of said high density multi-layered printed wiring board; and

a substrate supporter including;

a printed wiring board part consisting essentially of a resin material;

a window formed in said printed wiring board part and dimensioned for receipt of said high density multi-layered printed wiring board while a second side of said substrate, which is opposite to the first side of said substrate, is exposed from the window;

a plurality of bonding pads surrounding the window;

a second plurality of I/O terminals surrounding the group of said plurality of bonding pads; and

at least one conductive pattern for electrically connecting respective bonding pads and respective I/O terminals of said first plurality of and terminals, and

wherein the I/O terminals of said first plurality of I/O terminals of said build-up layer are electrically connected to the bonding pads on said substrate supporter.

7. A semiconductor package according to claim 6 wherein,

each of said interlayer insulations is made of a photosensitive epoxy resin.

8. A semiconductor package according to claim 6 wherein,

each of said conductive layers consists of a copper conductive layer and a groundwork layer placed between the copper conductive layer and one of said interlayer insulations, and wherein said groundwork layer includes a metal thin layer made of a metal selected from the group consisting of chrome, titanium and nickel.

9. A semiconductor package according to claim 6 wherein,

each of said conductive layers has a copper conductive layer;

wherein a metal cover layer is provided between a top surface of each copper conductive layer and a bottom surface of the interlayer insulation covering the copper conductive layer; and

wherein said metal cover layer is made of a metal which improves adhesion between a copper conductive layer and an interlayer insulation associated with the copper conductive layer.

10. A semiconductor package according to claim 9 wherein,

said cover layer is made of nickel.

11. A semiconductor package comprising:

a high density multi-layered printed wiring board including;

a substrate made of a material having a higher heat conductivity than that of resins;

a build-up layer formed on a first side of said substrate, said build-up layer being provided with interlayer insulations and conductive layers that are alternately laminated;

an electronic parts mounting area defined on a top surface of said build-up layer; and

a first plurality of I/O terminals provided, on the top surface of said build-up layer, at an area between said electronic parts mounting area and an edge of said substrate;

a plurality of electronic parts mounted on the electronic parts mounting area provided on said build-up layer of said high density multi-layered printed wiring board;

a lead frame provided with a plurality of leads surrounding an island supporting said high density multi-layered printed wiring board, said leads being electrically connected to the I/O terminals of said first plurality on said build-up layer; and

a resin molding for sealing electrical connections with a second side of said substrate exposed.

12. A semiconductor package according to claim 11 wherein,

each of said interlayer insulations is made of a photosensitive epoxy resin.

13. A semiconductor package according to claim 11 wherein,

each of said conductive layers consists of a copper conductive layer and a groundwork layer placed between the copper conductive layer and one of said interlayer insulations, and wherein said groundwork layer includes a metal thin layer made of a metal selected from the group consisting of chrome, titanium and nickel.

14. A semiconductor package according to claim 11 wherein, each of said conductive layers has a copper conductive layer;

wherein a metal cover layer is provided between a top surface of each copper conductive layer and a bottom surface of the interlayer insulation covering the copper conductive layer; and

wherein said metal cover layer is made of a metal which improves adhesion between a copper conductive layer and an interlayer insulation associated with the copper conductive layer.

15. A semiconductor package according to claim 14 wherein,

said cover layer is made of nickel.

16. A high density multi-layered printed wiring board comprising:

substrate having a higher heat conductivity than that of resins;

a build-up layer formed on a first side of said substrate and having interlayer insulations and conductive layers that are alternately laminateed;

an electronic parts mounting area defined on a top surface of said build-up layer;

a first plurality of I/O terminals provided on the top surface of said build-up layer;

a substrate supporter for mounting the multi-layered printed wiring board thereon and defining a window portion formed and dimensioned for supportive receipt of said high density multi-layered printed wiring board therein in a manner such that an opposite second side of said substrate is substantially exposed from the window, said substrate supporter including a second plurality of I/O terminals being electrically connected to said first plurality of I/O terminals.

17. The high density multi-layered printed wiring board as defined in claim 16 wherein, said first plurality of 110 terminals are positioned between said electronic parts mounting area and an edge of said substrate.

18. A high density multi-layered printed wiring board comprising:

a substrate having a higher heat conductivity than that of resins;

a build-up layer formed on a first side of said substrate and having interlayer insulations and conductive layers that are alternately laminated;

an electronic parts mounting area defined on a top surface of said build-up layer;

a first plurality of I/O terminals provided on the top surface of said build-up layer;

a lead frame including a plurality of leads, at least one of which being electrically connected to a respective I/O terminal of said first plurality of I/O terminals, and having an island member adapted to support the substrate thereon in a manner such that an opposite second side of said substrate is substantially exposed when mounted to said island member.

19. The high density multi-layered printed wiring board as defined in claim 18 further including:

a resin molding configured to seal electrical connections with a second side of the substrate while maintaining said substantial exposure thereof.

20. The high density multi-layered printed wiring board as defined in claim 18 wherein,

said island member defining a window portion enabling said substantial exposure of said second side of said substrate.

21. The high density multi-layered printed wiring board as defined in claim 20 wherein,

said lead frame defines an opening therethrough formed and dimensioned for receipt of the suspended substrate or said build-up layer therein.

22. The high density multi-layered printed wiring board as defined in claim 21 wherein,

said plurality of I/O terminals of said build-up layer are positioned between said electronic parts mounting area and an edge of said substrate.

23. The high density multi-layered printed wiring board as defined in claim 22 wherein,

said plurality of leads are positioned around said island member.