Single chip modules, repairable multichip modules, and methods of fabrication thereof

• US 5,841,193 A
• Filed: 05/20/1996
• Issued: 11/24/1998
• Est. Priority Date: 05/20/1996
• Status: Expired due to Term

• Current Assignee: EPIC Technologies Incorporated
• Original Assignee: EPIC Technologies Incorporated
• Inventors: Eichelberger, Charles William
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/650,628
• Time in Patent Office: 918 Days
• Field of Search: 257/723, 257/787, 257/724, 257/725, 257/726, 257/730, 257/773
• US Class Current: 257/723
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing

Abstract

Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric. Testing and repair of the module can be accomplished prior to or subsequent to fabrication of the multi-layer chip interconnect. Formation of multiple single chip modules is accomplished by singulating the multichip module into individual packages.

Claims

1. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;

a structural material surrounding and physically contacting the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said plurality of chips to form a second surface, said second surface comprising a back surface; and

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto.

2. The multichip module of claim 1, further comprising an intrachip metallization layer comprising metallization within each via opening electrically connected to a corresponding contact pad of said at least some contact pads, wherein metallization over each chip is isolated from metallization over each other chip of said plurality of chips such that said intrachip metallization layer fails to electrically interconnect any chips of said plurality of chips.

3. The multichip module of claim 1, further comprising a multi-layer structure disposed over said in situ processed layer, said multi-layer structure including a chip interconnect metallization layer electrically interconnecting at least some chips of said plurality of chips.

4. The multichip module of claim 3, wherein said multi-layer structure further comprises a release layer disposed over said in situ processed layer, said release layer being removable without removing said in situ processed layer, said release layer comprising one of a thermoplastic material or a solventable material.

5. The multichip module of claim 4, wherein said release layer comprises a thermoplastic transition layer disposed on said in situ processed layer, said release layer being removable with application of heat to said thermoplastic transition layer.

6. The multichip module of claim 3, wherein said multi-layer structure comprises a first multi-layer structure and is disposed over said in situ processed layer on said front surface, and said multichip module further comprises a second multi-layer structure disposed over said back surface.

7. The multichip module of claim 6, wherein said second multi-layer structure comprises a preprocessed printed circuit board conductively secured to said back surface.

8. The multichip module of claim 6, further comprising at least one conductive through connect disposed within said structural material and extending between said front surface and said back surface for facilitating electrical interconnection of said first multi-layer structure and said second multi-layer structure.

9. The multichip module of claim 8, further comprising at least one surface mount electronic component disposed on an exposed surface of at least one of said first multi-layer structure and said second multi-layer structure.

10. The multichip module of claim 9, wherein said at least one surface mount electronic component comprises a first surface mount electronic component disposed on an exposed surface of said first multi-layer structure and a second surface mount electronic component disposed on an exposed surface of said second multi-layer structure, said first surface mount electronic component and said second surface mount electronic component being electrically coupled through said at least one conductive through connect in said structural material.

11. The multichip module of claim 1, wherein at least one chip of said plurality of chips comprises a bare integrated circuit chip.

12. The multichip module of claim 1, wherein each chip of said plurality of chips comprises a bare integrated circuit chip.

13. The multichip module of claim 1, wherein said in situ processed layer disposed on said front surface comprises a photo-patternable dielectric material.

14. The multichip module of claim 13, wherein said structural material comprises a polymer consisting of one of epoxy, urethane and polyimide.

15. The multichip module of claim 1, wherein said structural material surrounds and physically contacts the at least one side surface of each chip so that there is no space between said structural material and said at least one side surface of each chip of said plurality of chips.

16. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;

a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said plurality of chips to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto; and

wherein said structural material has a thickness equal to a thickest chip of said plurality of chips such that the upper surface of the structural material is substantially co-planar with the upper surface of the thickest chip to form said first substantially co-planar surface, and such that a lower surface of the structural material is substantially co-planar with a lower surface of said thickest chip of said plurality of chips to form a second substantially co-planar surface, said second substantially co-planar surface comprising said back surface.

17. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;

a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said Plurality of chips to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto; and

wherein each chip of said plurality of chips has a common thickness, and wherein said structural material surrounding and mechanically interconnecting said chips in spaced planar relation comprises a thickness equal to said common thickness of said plurality of chips such that said second surface comprises a second substantially co-planar surface wherein the lower surface of said structural material is substantially co-planar with the lower surface of each chip of said plurality of chips, and wherein said first substantially co-planar surface comprising said front surface is parallel to said second substantially co-planar surface comprising said back surface.

18. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;

a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said plurality of chips to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto;

wherein each chip of said Plurality of chips comprises a bare integrated circuit chip; and

wherein each chip of said plurality of chips has an equal thickness such that the upper surface of each chip is co-planar with said front surface and the lower surface of each chip is co-planar with said back surface, said back surface comprising a planar main surface of the multichip module.

19. The multichip module of claim 18, further comprising a heat sink in physical contact with said back surface.

24. The integrated circuit chip module of claim 19, wherein said structural material surrounds and physically contacts the at least one side surface of said integrated circuit chip so that there is no space between said structural material and said at least one side surface of said integrated circuit chip.

20. An integrated circuit chip module comprising:

an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;

a structural material surrounding and physically contacting said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chip; and

a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip.

21. The integrated circuit chip module of claim 20, wherein said in situ processed layer comprises a photo-patternable dielectric material.

22. The integrated circuit chip module of claim 21, wherein said structural material comprises a polymer consisting of one of epoxy, urethane and polyimide.

23. The integrated circuit chip module of claim 21, wherein said metallization structure further comprises at least one input/output (I/O) contact at an exposed surface of said module, said at least one I/O contact being electrically coupled to said at least one contact pad of said integrated circuit chip, and being disposed at least partially over said structural material surrounding said at least one side of said integrated circuit chip.

25. An integrated circuit chip module comprising:

an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;

a structural material surrounding said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chin;

a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip;

wherein said in situ processed layer comprises a photo-patternable dielectric material; and

wherein said bottom surface is substantially co-planar with said lower surface of said integrated circuit chip.

26. An integrated circuit chip module comprising:

an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;

a structural material surrounding said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;

an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chip;

a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip;

wherein said in situ Processed layer comprises a photo-patternable dielectric material; and

wherein said back surface comprises an exposed planar main surface of said integrated circuit chip module.

27. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, and a lower surface; and

structural material surrounding and physically contacting the at least one side surface of each chip of said plurality of chips to mechanically interconnect in spaced planar relation said plurality of chips, said structural material having an upper surface co-planar with the upper surfaces of said plurality of chips, wherein a co-planar front surface is defined thereby, and wherein a lower surface of said structural material is substantially parallel with the lower surfaces of the plurality of chips, thereby defining a back surface.

28. The multichip module of claim 27, wherein each chip of said plurality of chips includes at least one contact pad at the upper surface thereof, said at least one contact pads being exposed at said co-planar front surface.

29. A multichip module comprising:

a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, and a lower surface;

structural material surrounding the at least one side surface of each chip of said Plurality of chips to mechanically interconnect in spaced planar relation said plurality of chips, said structural material having an upper surface co-planar with the upper surfaces of said plurality of chins, wherein a co-planar front surface is defined thereby, and wherein a lower surface of said structural material is substantially parallel with the lower surfaces of the plurality of chips, thereby defining a back surface; and

wherein the lower surface of the structural material is substantially co-planar with the lower surfaces of the plurality of chips.

30. The multichip module of claim 29, wherein said back surface is adhesively secured to a heat sink.