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Test mode power circuit for integrated-circuit chip

  • US 5,841,271 A
  • Filed: 08/06/1997
  • Issued: 11/24/1998
  • Est. Priority Date: 11/17/1993
  • Status: Expired due to Term
First Claim
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1. A power supply circuit for an integrated-circuit chip, comprising:

  • a first voltage reference source configured to output a first voltage reference V1;

    a second voltage reference source connected to receive the first voltage reference V1 from the first voltage reference source and to output a second voltage reference V2;

    a third voltage reference source connected to receive the first voltage reference V1 from the first voltage reference source and to output a third voltage reference V3, wherein the third voltage reference V3 is greater in magnitude than the second voltage reference V2;

    a first internal voltage generator connected to receive the second voltage reference V2 from the second voltage reference source and to output a first internal voltage Vint1;

    a second internal voltage generator connected to receive the third voltage reference V3 from the second voltage reference source and to output a second internal voltage Vint2, wherein the second internal voltage Vint2 is greater in magnitude than the first internal voltage Vint1;

    a comparator connected to receive a test voltage output from a test circuit and the first internal voltage Vint1 output from the first internal voltage generator, the comparator being powered by the first internal voltage Vint1 and being configured to produce a first output voltage VD1 that is based on a difference between the first internal voltage Vint1 and the test voltage;

    a first buffer amplifier connected to receive the first output voltage VD1 from the comparator and the second internal voltage Vint2 from the second internal voltage source, the first buffer amplifier being powered by the second internal voltage Vint2, the first buffer amplifier being configured to output a pair of voltages VD2 and VD3 which are based on the first output voltage VD1; and

    a second buffer amplifier connected to receive the pair of voltages VD2 and VD3 output by the first buffer amplifier, the second buffer amplifier further connected to receive an externally supplied voltage, the second buffer amplifier providing an output voltage Vo to the test circuit, the output voltage Vo being based on the pair of voltages VD2 and VD3.

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