Charge-based frequency locked loop and method

• US 5,841,324 A
• Filed: 06/20/1996
• Issued: 11/24/1998
• Est. Priority Date: 06/20/1996
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Williams, Brian Eric
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/671,781
• Time in Patent Office: 887 Days
• Field of Search: 331/14, 331/17, 331/27, 331/34, 331/36 R, 331/36 C
• US Class Current: 331/17
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A frequency locked loop (FLL) having an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of the oscillator. A switched reference capacitor provides a charge to the charge integrator which is a function of a reference frequency, so that the oscillator output frequency is a function of a product of the reference frequency times a ratio of the capacitance of the reference capacitor to the capacitance of the feedback capacitor. Plural reference capacitors, each responsive to a respective reference frequency may be provided so that the oscillator output frequency can be related to the sums or differences of the reference frequencies, the ratios of capacitors, the ratio of the reference voltages or a fixed multiplication factor.

Claims

1. A frequency locked loop (FLL) comprising:

a charge integrating amplifier;

a voltage controlled oscillator which operates in response to an output voltage from said amplifier;

a switched-capacitor circuit for providing an input current to said amplifier which is a function of a combination of a reference current related to a reference frequency and a feedback current related to an output frequency of said voltage controlled oscillator,

whereby the input current varies in response to the output frequency to lock the FLL on a frequency.

2. The FLL of claim 1 wherein said switched-capacitor circuit comprises a reference capacitor for being switched at the reference frequency, a feedback capacitor for being switched at the output frequency, and circuit means for combining charges moved by said reference and feedback capacitors and for providing the combined charges as the input current to said amplifier,

whereby the output frequency is a function of a product of the reference frequency times a ratio of the capacitance of said reference capacitor and the capacitance of said feedback capacitor.

3. The FLL of claim 2 further comprising a first reference voltage for charging said reference capacitor and a second reference voltage for charging said feedback capacitor, wherein a ratio of the first reference voltage to the second reference voltage is one of (a) an inverse of the ratio of the capacitance of said reference capacitor to the capacitance of said feedback capacitor, and (b) one.

4. The FLL of claim 2 further comprising a first reference voltage for charging said reference capacitor and a second reference voltage for charging said feedback capacitor, wherein magnitudes of the first and second reference voltages determine a bandwidth of the FLL.

5. The FLL of claim 4 wherein the output frequency is independent of changes in the bandwidth of the FLL when the magnitudes of the first and second reference voltages are scaled by the same factor.

6. A charge-based frequency locked loop (FLL) comprising an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of said oscillator.

7. The FLL of claim 6 further comprising a switched reference capacitor for providing a charge to said charge integrator which is a function of a reference frequency, wherein said oscillator output frequency is a function of a product of the reference frequency times a first ratio of the capacitance of said reference capacitor to the capacitance of said feedback capacitor.

8. The FLL of claim 7 further comprising a first reference voltage for charging said reference capacitor and a second reference voltage for charging said feedback capacitor, wherein said oscillator output frequency is further a function of a second ratio of the first reference voltage to the second reference voltage.

9. The FLL of claim 8 wherein a product of the first and second ratios is one.

10. The FLL of claim 8 wherein the second ratio is one.

11. The FLL of claim 6 further comprising plural switched reference capacitors, each for moving a charge responsive to respective reference frequencies, and circuit means for providing a combination of the moved charges and charge provided by said feedback capacitor to said charge integrator.

12. The FLL of claim 11 further comprising a divider for said oscillator output frequency, and wherein said oscillator output frequency is a function of a divisor from said divider and a ratio of (a) a combination of a capacitance of a first said reference capacitor times its respective said reference frequency and a capacitance of a second said reference capacitor times its respective said reference frequency to (b) a capacitance of said switched feedback capacitor.

13. The FLL of claim 12 comprising three said reference capacitors which are arranged so that said combination is a sum of the capacitance of the first said reference capacitor times its respective said reference frequency and the capacitance of the second said reference capacitor times its respective said reference frequency minus a capacitance of a third said reference capacitor times its respective said reference frequency.

14. The FLL of claim 11 wherein said plural switched reference capacitors are arranged so that said oscillator output frequency is a function of a difference between a capacitance of a first said reference capacitor times its respective said reference frequency and a capacitance of a second said reference capacitor times its respective said reference frequency.

15. The FLL of claim 11 wherein said plural switched reference capacitors are arranged so that said oscillator output frequency is a function of a sum of a capacitance of a first said reference capacitor times its respective said reference frequency and a capacitance of a second said reference capacitor times its respective said reference frequency.

16. A method of frequency locking a frequency of an output from an oscillator comprising the steps of using an output frequency from the oscillator to control the amount of charge provided by a switched feedback capacitor to a charge integrator, and using an output voltage of the charge integrator to control the output frequency of the oscillator.

17. The method of claim 16 further comprising the step of providing a charge from a switched reference capacitor to the charge integrator which is a function of a reference frequency, so that the oscillator output frequency is a function of a product of the reference frequency times a first ratio of the capacitance of the reference capacitor to the capacitance of the feedback capacitor.

18. The method of claim 17 further comprising the step of charging the reference capacitor with a first reference voltage and charging the feedback capacitor with a second reference voltage, so that the oscillator output frequency is further a function of a second ratio of the first reference voltage to the second reference voltage.

19. The method of claim 17 further comprising the steps of charging the reference capacitor with a first reference voltage and charging the feedback capacitor with a second reference voltage, and setting a loop bandwidth by adjusting magnitudes of the first and second reference voltages.

20. The method of claim 19 further comprising the step of scaling the magnitudes of the first and second reference voltages by the same factor so that the output frequency is independent of changes in the loop bandwidth.

21. The method of claim 20 further comprising the step of providing the first and second reference voltages so that a product of the first and second ratios is one.

22. The method of claim 20 further comprising the step of providing equal first and second reference voltages.

23. The method of claim 16 further comprising the step of providing charges from plural switched reference capacitors to the charge integrator, the amount of each of the charges being responsive to respective reference frequencies.

24. The method of claim 23 further comprising the step of multiplying the oscillator output frequency by a factor, so that the oscillator output frequency is a function of the factor times a ratio of (a) a combination of a capacitance of a first reference capacitor times its respective reference frequency and a capacitance of a second reference capacitor times its respective reference frequency to (b) a capacitance of the switched feedback capacitor.

25. The method of claim 24 comprising the step of arranging three of the reference capacitors so that the combination is a sum of the capacitance of the first reference capacitor times its respective reference frequency and the capacitance of the second reference capacitor times its respective reference frequency minus a capacitance of a third reference capacitor times its respective reference frequency.

26. A method of setting a bandwidth of a frequency locked loop (FLL) independently of an output frequency of an oscillator in the FLL, the method comprising the steps of:

(a) using an output frequency from the oscillator to control the amount of charge provided by a switched feedback capacitor to a charge integrator;

(b) providing a charge from a switched reference capacitor to the charge integrator which is a function of a reference frequency;

(c) using an output voltage of the charge integrator to control the output frequency of the oscillator;

(d) charging the reference capacitor with a first reference voltage and charging the feedback capacitor with a second reference voltage;

(e) setting a bandwidth of the FLL by adjusting magnitudes of the first and second reference voltages; and

(f) scaling the magnitudes of the first and second reference voltages by the same factor so that the output frequency is independent of changes in the loop bandwidth.