Fast testing of D/A converters

• US 5,841,382 A
• Filed: 03/19/1997
• Issued: 11/24/1998
• Est. Priority Date: 03/19/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Burchanowski, William E., Khoini-Poorfard, Ramin, Walden, Robert W.
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/820,819
• Time in Patent Office: 615 Days
• Field of Search: 341/120, 341/118, 341/144
• US Class Current: 341/120
• CPC Class Codes: H03M 1/109 for dc performance, i.e. static testing H03M1/1085 takes precedence
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.

Claims

1. An integrated circuit having a D/A converter, comprising:

(a) a plurality of resistors configured in a resistor string and adapted to receive two reference voltages;

(b) a plurality of switches connected to the plurality of resistors;

(c) decoder circuitry adapted to control the switches based on a code value to generate a corresponding tap voltage;

(d) an output amplifier configured to generate an analog output voltage based on the tap voltage;

(e) a normal-mode capacitor coupled to an input of the output amplifier to reduce power consumption during normal-mode operation of the D/A converter; and

(f) a test-mode capacitor switchably coupled to the normal-mode capacitor to reduce settling time during test-mode operation of the D/A converter.

2. The invention of claim 1, wherein the resistor string is a folded resistor string or a linear resistor string.

3. The invention of claim 1, further comprising a switch transistor configured to control the configuration of the test-mode capacitor between test-mode operation and normal-mode operation.

4. The invention of claim 1, further comprising a power-saving transistor configured to isolate the signal stored in the normal-mode capacitor during normal-mode operation to permit powering down of the two reference voltages when the code value does not change.

5. The invention of claim 1, wherein the size of the normal-mode capacitor is greater than the size of the test-mode capacitor.

6. The invention of claim 1, wherein, during test-mode operation, the duration of each test step is a function of the code value.

7. The invention of claim 1, wherein, during test-mode operation, non-consecutive code values are used for consecutive test steps and the duration of each test step corresponds to a partial settling time for the D/A converter.

8. The invention of claim 7, wherein, during test-mode operation, the duration of each test step is a function of the code value.

9. The invention of claim 8, wherein:

the resistor string is a folded resistor string or a linear resistor string; and

further comprising;

a switch transistor configured to control the configuration of the test-mode capacitor between test-mode operation and normal-mode operation; and

a power-saving transistor configured to isolate the signal stored in the normal-mode capacitor during normal-mode operation to permit powering down of the two reference voltages when the code value does not change, wherein the size of the normal-mode capacitor is greater than the size of the test-mode capacitor.

10. A method for testing a D/A converter, comprising the steps of:

(a) applying a sequence of code values to the D/A converter, wherein the duration that each code value is applied to the D/A converter is a function of each code value and the duration is independent of the output signal generated by the D/A converter; and

(b) measuring an analog output voltage from the D/A converter after the corresponding duration for each code value.

11. The invention of claim 10, wherein the sequence of code values corresponds to non-consecutive code values.

12. The invention of claim 10, wherein the duration that each code value is applied to the D/A converter corresponds to a partial settling time for the D/A converter.

13. The invention of claim 10, wherein step (b) comprises the step of comparing the analog output voltage to a variable voltage threshold value.

14. A method for testing a D/A converter, comprising the steps of:

(a) applying a sequence of non-consecutive code values to the D/A converter, wherein the duration that each code value is applied to the D/A converter corresponds to a partial settling time for the D/A converter; and

(b) measuring an analog output voltage from the D/A converter after the corresponding duration for each code value.

15. The invention of claim 14, wherein step (b) comprises the step of comparing the analog output voltage to a variable voltage threshold value.

16. The invention of claim 14, wherein the duration that each code value is applied to the D/A converter is a function of each code value.

17. The invention of claim 14, wherein the duration that each code value is applied to the D/A converter is a function of each code value and is independent of the output signal generated by the D/A converter.