Multiprocessor graphics system

• US 5,841,444 A
• Filed: 03/21/1997
• Issued: 11/24/1998
• Est. Priority Date: 03/21/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Mun, Byung-in, Eo, Kil-Su
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/823,041
• Time in Patent Office: 613 Days
• Field of Search: 345/502, 345/505, 345/506, 345/507-509, 345/511, 395/306, 395/200.3, 395/200.5, 395/200.81, 395/800.11, 395/800.14
• US Class Current: 345/506
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A multiprocessor graphics system having a pixel link architecture, includes: 1) a plurality of sub-graphics systems each of which assigned to each of a plurality of sub-screens provided by sectioning a display screen; and 2) a ring network for connecting the plurality of sub-graphics systems. Each of the sub-graphics systems includes a geometry engine, a raster engine, a local frame buffer and a pixel distributor. An interconnection network bottleneck between the raster engine and frame buffer is removed and a conventional memory system can be used by reducing the number of data transmissions between the raster engine and frame buffer while maintaining image parallelism and object parallelism.

Claims

1. A multiprocessor graphics system having a pixel link architecture, comprising:

a plurality of sub-graphics systems each assigned to each of a plurality of sub-screens provided by sectioning a display screen; and

a ring network for connecting said plurality of sub-graphics systems,

wherein each of said sub-graphics systems comprises;

a geometry engine for receiving three dimensional object data from a host processor and performing a floating point operation including transformation, lighting of reflecting the effect of light on color, clipping, perspective projection and triangle division;

a raster engine for calculating the color value, a z-depth value and coordinates of each pixel processed in the geometry engine and performing triangle rasterization, interpolation and bit block transmission;

a local frame buffer for storing data belonging to a sub-screen assigned to said local frame buffer; and

a pixel distributor for receiving data processed in said raster engine, checking a pixel address, storing said data in said local frame buffer if said pixel address belongs to its own local frame section, and transmitting said data to another sub-graphics system via said ring network if said pixel address does not belong to its own local frame section.

2. A multiprocessor graphics system having pixel link architecture according to claim 1, wherein said ring network is a duplex linked ring network for transmitting said data clockwise and counterclockwise and said pixel distributor controls transmission of said data so that said data is transmitted via an optimally short path in said duplex linked network when said data is transmitted to another sub-graphics system.

3. A multiprocessor graphics system having pixel link architecture according to claim 1, wherein said ring network transmits said data by using a token.

4. A multiprocessor graphics system having pixel link architecture according to claim 2, wherein said ring network transmits said data by using a token.

5. A multiprocessor graphics system, comprising:

a plurality of sub-graphics systems each assigned to each of a plurality of sub-screens provided by sectioning a display screen; and

a ring network for connecting said plurality of sub-graphics systems,

wherein each of said sub-graphics systems comprises;

a geometry engine for processing pixel data and outputting a first processing result;

a raster engine for processing the first processing result output by said geometry engine and outputting a second processing result;

a local frame buffer for storing data belonging to a sub-screen assigned to said local frame buffer; and

a pixel distributor for receiving said second processing result output by said raster engine and performing one of storing said data in said local frame buffer and transmitting said data to another sub-graphics system via said ring network according to a pixel address associated with said second processing result.

6. A multiprocessor graphics system having pixel link architecture according to claim 5, wherein said ring network is a duplex linked ring network for transmitting said data clockwise and counterclockwise and said pixel distributor controls transmission of said data so that said data is transmitted via an optimally short path in said duplex linked network when said data is transmitted to another sub-graphics system.

7. A multiprocessor graphics system having pixel link architecture according to claim 5, wherein said ring network transmits said data by using a token.

8. A multiprocessor graphics system having pixel link architecture according to claim 6, wherein said ring network transmits said data by using a token.