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Transition aligned video synchronization system

  • US 5,841,482 A
  • Filed: 12/16/1996
  • Issued: 11/24/1998
  • Est. Priority Date: 08/01/1995
  • Status: Expired due to Term
First Claim
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1. A synchronization circuit comprising:

  • a plurality of delay line sections connected in series to form a delay line, each delay line section having a plurality of taps, wherein a clock signal applied to an end of the delay line provides a series of delayed signals at the taps, each delay line section delays the clock signal by less than a period of the clock signal, and the delay line delays the clock signal by more than the period of the clock signal;

    a plurality of selection units each coupled to taps in a corresponding delay line section, wherein each selection unit selects from among a plurality of delayed signals at the taps in the corresponding delay line section, and in response to one of the delayed signals having a desired phase relative to a transition in a reference signal, generates an output signal from that delayed signal; and

    a selection circuit which selects one of the output signals of the selection units and generates an output clock signal from the selected output signal.

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