Transition aligned video synchronization system

• US 5,841,482 A
• Filed: 12/16/1996
• Issued: 11/24/1998
• Est. Priority Date: 08/01/1995
• Status: Expired due to Term

• Current Assignee: Creative Technology Ltd.
• Original Assignee: Auravision Corporation
• Inventors: King, Sherman Tan, Wang, Niantsu N., Hwang, Guorjuh T.
• Primary Examiner(s): LEE, MICHAEL
• Application Number:
  US08/768,361
• Time in Patent Office: 708 Days
• Field of Search: 348/512, 348/513, 348/515, 348/516, 348/518, 348/536, 348/537, 348/510
• US Class Current: 348/537
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

Claims

1. A synchronization circuit comprising:

a plurality of delay line sections connected in series to form a delay line, each delay line section having a plurality of taps, wherein a clock signal applied to an end of the delay line provides a series of delayed signals at the taps, each delay line section delays the clock signal by less than a period of the clock signal, and the delay line delays the clock signal by more than the period of the clock signal;

a plurality of selection units each coupled to taps in a corresponding delay line section, wherein each selection unit selects from among a plurality of delayed signals at the taps in the corresponding delay line section, and in response to one of the delayed signals having a desired phase relative to a transition in a reference signal, generates an output signal from that delayed signal; and

a selection circuit which selects one of the output signals of the selection units and generates an output clock signal from the selected output signal.

2. The synchronization circuit of claim 1, wherein each selection unit comprises control logic which asserts a control signal to indicate that one of the delayed signals in the corresponding delay line section has the desired phase, wherein the selection circuit selects from among the output signals of selection units having asserted control signals.

3. The synchronization circuit of claim 2, wherein each selection unit comprises a series of latches, each latch coupled to a corresponding tap in the corresponding delay line section, wherein the transition in the reference signal triggers the latches and causes each latch to store a value which indicates a voltage at the corresponding tap when the latch was triggered.

4. The synchronization circuit of claim 3, further comprising a reference signal generator which generates one reference signal per the selection unit and simultaneously applies the reference signals to corresponding selection units.

9. The synchronization circuit of claim 1, further comprising a deglitching circuit coupled to the output clock signal, wherein the deglitching circuit generates from the output clock signal a second output clock signal whose periods are more regular than the output clock signal.

5. A synchronization circuit comprising:

a delay line which includes;

delay elements connected in series;

a first plurality of taps which are separated from each other by delay elements; and

a second plurality of taps which are separated from each other by delay elements, wherein

taps in the first plurality are interwoven with taps in the second plurality and each tap in the first plurality is separated from each tap in the second plurality of taps by at least one delay element;

a series of latches, each latch having an input terminal coupled to a corresponding tap in the first plurality, wherein in response to a transition in a reference signal, each latch stores a value indicating a voltage level at the corresponding tap;

a series of gates, each gate having an input terminal coupled to a corresponding tap in the second plurality; and

selection logic which selects a tap in the second plurality and causes the gate connected to the selected tap to conduct a signal from the delay line, the selected tap being between a first tap which is coupled to a first latch storing a first value and a second tap which is coupled to a second latch storing a second value.

6. The synchronization circuit of claim 5, wherein each delay element comprises an inverter.

7. The synchronization circuit of claim 5, wherein each gate comprises a pass gate.

8. The synchronization circuit of claim 5, wherein:

the delay line is partitioned into a plurality of delay line sections wherein each delay line section comprises a plurality of delay elements, wherein the delay line provides a total delay which is greater than one period of a clock signal applied to the delay line and each delay line section provides a delay which is less than one period of the clock signal;

the selection logic is partitioned into a plurality of selection units, wherein each selection unit has a corresponding delay line section and causes at most one gate coupled to the corresponding delay line section to conduct at a time; and

the selection logic further comprises a selection circuit which selects as an output clock signal one of the signals conducted by the gates.