Integrated circuit I/O using a high performance bus interface

• US 5,841,580 A
• Filed: 02/10/1997
• Issued: 11/24/1998
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/798,520
• Time in Patent Office: 652 Days
• Field of Search: 395/290, 395/856, 395/292, 395/828, 395/297, 395/298, 395/309, 395/310, 365/189.12, 365/230.03, 365/194, 365/240
• US Class Current: 365/194
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A computer system comprising:

a bus;

a semiconductor device coupled to the bus, the semiconductor device comprising an access-time register operative to store a value indicative of a delay time for the semiconductor device to respond to a bus transaction request; and

a bus master coupled to the bus, the bus master transmitting the value and the bus transaction request to the semiconductor device via the bus, wherein the semiconductor device responds to the bus transaction request after the delay time.

2. The computer system of claim 1, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.

3. A semiconductor device receiving a bus transaction request from a bus, the semiconductor device comprising:

a plurality of conductors coupling the semiconductor device to the bus to receive the bus transaction request; and

interface circuitry coupled to the plurality of conductors and including at least one access-time register operative to store a value indicative of a delay time for the semiconductor device, wherein the semiconductor device responds to the bus transaction request after the delay time.

4. The semiconductor device of claim 3, wherein the semiconductor device is a memory device.

5. The semiconductor device of claim 3, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.

6. A method for programming a semiconductor device, comprising:

writing a value to an access-time register of the semiconductor device, the value specifying a delay time for the semiconductor device;

receiving a bus transaction request; and

responding to the bus transaction request after the delay time.

7. The method of claim 6, wherein the semiconductor device is a memory device.

8. A memory device, comprising:

an array of memory cells connected in rows and columns;

a plurality of conductors for coupling to an external bus and for carrying address information and data information; and

interface circuitry coupled to the plurality of conductors and the array of memory cells for accessing the array of memory cells in response to the address information received from the plurality of conductors, the interface circuitry including an access-time register for storing the data information that defines an access time of the array of memory cells.

9. The memory device of claim 8, wherein the interface circuitry comprises a plurality of registers including a plurality of access-time registers, and wherein the plurality of conductors carries control information for selecting the access-time register from the plurality of access-time registers.

10. The memory device of claim 8, wherein address information specifying the access-time register and control information specifying an access-time register operation are received from the plurality of conductors, wherein the data information that defines the access time of the array of memory cells is loaded into the access-time register from the plurality of conductors in response to the address and control information received for the access-time register operation.

11. The memory device of claim 8, wherein the memory device is a dynamic random access memory device (DRAM).

12. The memory device of claim 8, wherein the memory device waits a time equal to the access time before accepting data for the array of memory cells from the plurality of conductors.

13. The memory device of claim 8, wherein the memory device waits a time equal to the access time before supplying data from the array of memory cells to the plurality of conductors.

14. A memory device comprising:

at least one memory section; and

a device interface coupling the memory section to a bus, the device interface receiving a bus transaction request from the bus, the device interface comprising at least one register including an access-time register whose contents indicate a delay time after which the memory device responds to the bus transaction request.

15. The memory device of claim 14, wherein the transaction request information includes control information specifying a particular access-time register within the memory device for determining the delay time at which the memory device responds to the bus transaction request.

16. The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a row address strobe access time.

17. The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a page-mode access time.

18. The memory device of claim 14, wherein the memory section is a dynamic memory section and the delay time is at least a normal-mode access time.

19. The memory device of claim 14, wherein the delay time is a fixed number of cycles for accessing the at least one register.

20. The memory device of claim 19, wherein the fixed number of cycles is eight.

21. The memory device of claim 14, wherein the delay time is selected from a set of delay times such that the semiconductor device responds to the bus transaction request after a predetermined period of time.

22. A system comprising:

a bus;

a first memory device comprising;

a first memory section;

a first device interface coupling the first memory section to the bus, the first device interface receiving a first bus transaction request from the bus, the first device interface including a first access-time register whose contents indicate a first delay time after which the first memory device responds to the first bus transaction request; and

a second memory device comprising;

a second memory section;

a second device interface coupling the second memory section to the bus, the second device interface receiving a second bus transaction request from the bus, the second device interface including a second access-time register whose contents indicate a second delay time after which the second memory device responds to the second bus transaction request, wherein the first memory device is capable of transferring information on the bus during the second delay time of the second memory device.