System and method for processing graphic delay data of logic circuit to reduce topological redundancy
First Claim
1. A system for processing data representing delays in a logic network, comprising:
- a data holding means for holding a first set of graphic data representing a first delay network composed of;
a first set of vertices comprising a first vertex, a second vertex, a third vertex, and a fourth vertex, anda first set of weighted directional edges extending between elements of the first set of vertices and containing a first directional edge extending from the first vertex to the fourth vertex having a weight x1, a second directional edge extending from the second vertex to the third vertex having a weight x2, a third directional edge extending from the first vertex to the third vertex having a weight p1, and a fourth directional edge extending from the second vertex to the fourth vertex having a weight p2;
means for determining that the first set of delay data meets the condition (x1+x2)=(p1+p2); and
a data processing means for processing the first set of graphic data to obtain a second set of graphic data representing a second delay network composed of;
a second set of vertices comprising the first vertex, the second vertex, the third vertex, the fourth vertex, and a fifth vertex not contained in the first set of vertices, anda second set of weighted directional edges extending between elements of the second set of vertices and containing a fifth directional edge extending from the first vertex to the fifth vertex having a weight of zero, a sixth directional edge extending from the second vertex to the fifth vertex having a weight (x2-p1), a seventh directional edge extending from the fifth vertex to the third vertex having a weight p1, and an eighth directional edge extending from the fifth vertex to the fourth vertex having a weight x1.
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Abstract
A delay network of logic circuit delay data composed of a first set of vertices containing first to fourth vertices, and a first set of weighted directional edges containing a first directional edge extending from the first vertex to the fourth vertex, a second directional edge extending from the second vertex to the third vertex, a third directional edge extending from the first vertex to the third vertex, and a fourth directional edge extending from the second vertex to the fourth vertex, is converted into a delay network composed of a second set of vertices containing the first to fourth vertices and an added fifth vertex, and a second set of weighted directional edges containing a fifth directional edge extending from the first vertex to the fifth vertex, a sixth directional edge extending from the second vertex to the fifth vertex, a seventh directional edge extending from the fifth vertex to the third vertex, and an eighth directional edge extending from the fifth vertex to the fourth vertex.
52 Citations
42 Claims
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1. A system for processing data representing delays in a logic network, comprising:
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a data holding means for holding a first set of graphic data representing a first delay network composed of; a first set of vertices comprising a first vertex, a second vertex, a third vertex, and a fourth vertex, and a first set of weighted directional edges extending between elements of the first set of vertices and containing a first directional edge extending from the first vertex to the fourth vertex having a weight x1, a second directional edge extending from the second vertex to the third vertex having a weight x2, a third directional edge extending from the first vertex to the third vertex having a weight p1, and a fourth directional edge extending from the second vertex to the fourth vertex having a weight p2; means for determining that the first set of delay data meets the condition (x1+x2)=(p1+p2); and a data processing means for processing the first set of graphic data to obtain a second set of graphic data representing a second delay network composed of; a second set of vertices comprising the first vertex, the second vertex, the third vertex, the fourth vertex, and a fifth vertex not contained in the first set of vertices, and a second set of weighted directional edges extending between elements of the second set of vertices and containing a fifth directional edge extending from the first vertex to the fifth vertex having a weight of zero, a sixth directional edge extending from the second vertex to the fifth vertex having a weight (x2-p1), a seventh directional edge extending from the fifth vertex to the third vertex having a weight p1, and an eighth directional edge extending from the fifth vertex to the fourth vertex having a weight x1. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for processing data representing delays in a logic network, comprising the steps of:
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holding a first set of graphic data representing a first delay network composed of; a first set of vertices comprising a first vertex, a second vertex, a third vertex, and a fourth vertex, and a first set of weighted directional edges extending between elements of the first set of vertices and containing a first directional edge extending from the first vertex to the fourth vertex having a weight x1, a second directional edge extending from the second vertex to the third vertex having a weight x2, a third directional edge extending from the first vertex to the third vertex having a weight p1, and a fourth directional edge extending from the second vertex to the fourth vertex having a weight p2; determining that the first set of delay data meets the condition (x1+x2)=(p1+p2); and processing the first set of graphic data to obtain a second set of graphic data representing a second delay network composed of; a second set of vertices comprising the first vertex, the second vertex, the third vertex, the fourth vertex, and a fifth vertex not contained in the first set of vertices, and a second set of weighted directional edges extending between elements of the second set of vertices and containing a fifth directional edge extending from the first vertex to the fifth vertex having a weight of zero, a sixth directional edge extending from the second vertex to the fifth vertex having a weight (x2-p1), a seventh directional edge extending from the fifth vertex to the third vertex having a weight p1, and an eighth directional edge extending from the fifth vertex to the fourth vertex having a weight x1. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A logic circuit delay data holding system for holding a set of delay data of a target logic circuit having a multiplicity of inputs and a multiplicity of outputs, the system comprising:
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a delay network generation means for responding to set of constitutional data of the logic circuit to generate delay network composed of; a plurality of source vertices corresponding to a plurality of input terminals of the logic circuit, a plurality of sink vertices corresponding to a plurality of output terminals of the logic circuit, a plurality of internal vertices lying on a plurality of paths connecting the source vertices with the sink vertices, and a plurality of directional edges each interconnecting two of the source, sink and internal vertices, the directional edges being each weighted so that a largest weighted path length between any concerned one of the source vertices and any concerned one of the sink vertices is in accord with a delay time between a corresponding one of the input terminals of the logic circuit and a corresponding one of the output terminals of the logic circuit; a delay network hold means for holding the set of delay data, as it represents the delay network; and a delay network transform means for transforming the delay network to reduce a quantity of the delay data in the delay network hold means so that all paths of the delay network are represented and the largest weighted path length between the concerned source vertex and the concerned sink vertex is in accord with the delay time between the corresponding input terminal of the logic circuit and the corresponding output terminal of the logic circuit. - View Dependent Claims (37, 38, 39, 40, 41, 42)
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36. A logic circuit delay data holding method for holding a set of delay data of a logic circuit with a multiplicity of inputs and a multiplicity of outputs, the logic circuit being a target of a delay computation, the method comprising:
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a first step of responding to a set of constitutional data of the logic circuit to generate a delay network including; a plurality of source vertices corresponding to a plurality of input terminals of the logic circuit, a plurality of sink vertices corresponding to a plurality of output terminals of the logic circuits, and a plurality of paths cooperatively connecting the source vertices with the sink vertices, the plurality of paths consisting of a plurality of directional edges each weighted so that a total weight along a most-weighted path between any concerned one of the source vertices and any concerned one of the sink vertices is in accord with a delay time between one of the input terminals corresponding to the concerned source vertex and one of the output terminals corresponding to the concerned sink vertex; a second step of holding the set of delay data, as it represents the delay network; and a third step of transforming the delay network to reduce a quantity of the delay data so that all paths of the delay network are represented and the total weight along the most-weighted path between the concerned source vertex and the concerned sink vertex is kept in accord with the delay time between said one of the input terminals corresponding to the concerned source vertex and said one of the output terminals corresponding to the concerned sink vertex.
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Specification