Apparatus and method of filtering a signal utilizing recursion and decimation

• US 5,841,681 A
• Filed: 07/08/1996
• Issued: 11/24/1998
• Est. Priority Date: 04/10/1996
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Hwan-Rei, Jen, Chein-Wei, Chen, Yung-Lung, Tai, Chiao-Yen
• Primary Examiner(s): Gordon, Paul P.
• Assistant Examiner(s): Dolan, Robert J.
• Application Number:
  US08/679,430
• Time in Patent Office: 869 Days
• Field of Search: 364/724.011, 364/724.013, 364/724.06, 364/724.13, 364/724.1, 704/203, 704/204, 704/205, 324/76.31, 375/350
• US Class Current: 708/300
• CPC Class Codes: H03H 17/0266 Filter banks

Abstract

Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Claims

1. A digital signal filter bank device for filtering an external input signal to generate a filtered digital output signal, the device comprising:

input signal selector means for selecting between the external input signal and a low-pass filtered feedback signal to provide a filter input signal;

filter bank means for receiving the filter input signal and for filtering the filter input signal to concurrently generate both a high-pass filtered signal and a low-pass filtered signal, the low-pass filtered signal including a low-pass filtered output signal and the low-pass filtered feedback signal; and

frequency band select means for receiving both the high-pass filtered signal and the low-pass filtered output signal directly from the filter bank means for generating the filtered digital output signal;

wherein the filter bank means includes means for applying a distributed arithmetic algorithm to the filter input signal to generate first and second summations of product terms respectively representing the high-pass filtered signal and the low-pass filtered signal; and

wherein the filter bank means further includes low-pass filter means for generating the low-pass filtered feedback signal using a decimated sampling rate.

2. The digital signal filter bank device of claim 1, wherein the filter bank means includes a plurality of filter means organized as a plurality of banks of filter means, wherein the plurality of filter means generates a plurality of filtered outputs having a plurality of frequency bands, and wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

3. The digital signal filter bank device of claim 1, further comprising analog-to-digital converter means for converting the external input signal to a digital format for processing by the input signal selector means.

4. The digital signal filter bank device of claim 1,

wherein the input signal selector means includes first and second arrays of tri-state buffer means having respective first and second output lines,

wherein the first and second output lines are tied to form a selector output line to carry the filter input signal,

wherein the first array of tri-state buffer means includes a first input for receiving the external input signal,

wherein the second array of tri-state buffer means includes a second input for receiving the low-pass filtered feedback signal, and

wherein the first and second arrays of tri-state buffer means include an output enable input to control selection between the external input signal and the low-pass filtered feedback signal to provide the filter input signal.

5. The digital signal filter bank device of claim 1,

wherein the low-pass filtered feedback signal is a plurality of feedback signals,

wherein the input signal selector means includes a first plurality of arrays of tri-state buffer means having a first plurality of output lines, the first plurality of arrays including

a first array of tri-state buffer means having a corresponding first output line, and

a second plurality of arrays of tri-state buffer means having a respective second plurality of output lines,

wherein the first plurality of output lines are tied to form a selector output to carry the filter input signal,

wherein the first array of tri-state buffer means includes a first input for receiving the external input signal,

wherein the second plurality of arrays each includes a second input for receiving a corresponding one of the plurality of feedback signals, and

wherein the first plurality of arrays of tri-state buffer means includes an output enable input to control selection between the external input signal and the plurality of feedback signals to provide the filter input signal.

6. The digital signal filter bank device of claim 1,

wherein the frequency band select means includes first and second arrays of tri-state buffer means having respective first and second output lines,

wherein the first and second output lines are tied to form a device output to carry the device output signal,

wherein the first array of tri-state buffer means includes a first input for receiving the high-pass filtered signal,

wherein the second array of tri-state buffer means includes a second input for receiving the low-pass filtered signal, and

wherein the first and second arrays of tri-state buffer means include respective first and second output enable inputs to independently control respective selection of the high-pass filtered signal and the low-pass filtered signal for transmission on the device output.

7. The digital filter bank device of claim 6, wherein the low-pass filtered output signal is one of a sequence of low-pass filtered feedback signals and the low-pass filtered signal received by the second array of tri-state buffer means is a final low-pass filtered feedback signal in the sequence of low-pass filtered feedback signals.

8. The digital signal filter bank device of claim 1, wherein the filter bank means includes a plurality of filters means organized as one bank of filter means, wherein the plurality of filter means generates a plurality of filtered outputs having a plurality of frequency bands, wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

9. The digital signal filter bank device of claim 8, wherein the plurality of filter means includes a high-pass filter means for generating the high-pass filtered signal and a low-pass filter means for generating the low-pass filtered signal.

10. The digital signal filter bank device of claim 9, wherein the high-pass filter means and the low-pass filter means simultaneously receive the filter input signal.

11. The digital signal filter bank device of claim 8, wherein the plurality of filter means includes high-pass filter means for generating the high-pass filtered signal, low-pass filter means for generating the low-pass filtered signal, and a plurality of band-pass filter means for generating a plurality of band-pass filtered signals and wherein the frequency band select means is further responsive to the plurality of band-pass filtered signals for generating the filtered digital output signal.

12. The digital signal filter bank device of claim 11, wherein the high-pass filter means, the low-pass filter means, and the plurality of band-pass filter means simultaneously receive the filter input signal.

13. The digital signal filter bank device of claim 11,

wherein the frequency band select means includes a first plurality of arrays of tri-state buffer means having a plurality of output lines, the first plurality of arrays of tri-state buffer means including

a first array of tri-state buffer means,

a second array of tri-state buffer means, and

a second plurality of arrays of tri-state buffer means,

wherein the plurality of output lines are tied to form a device output to carry the device output signal,

wherein the first array of tri-state buffer means includes a first input for receiving the high-pass filtered signal,

wherein the second array of tri-state buffer means includes a second input for receiving the low-pass filtered signal,

wherein the second plurality of arrays of tri-state buffer means each includes a third input for receiving a corresponding one of the plurality of band-pass filtered signals, and

wherein the first plurality of arrays of tri-state buffer means include a plurality of respective output enable inputs to independently control respective selection of the high-pass filtered signal, low-pass filtered signal, and plurality of band-pass filtered signals for transmission on the device output.

14. The digital filter bank device of claim 13, wherein the low-pass filtered output signal is one of a sequence of low-pass filtered feedback signals and the low-pass filtered signal received by the second array of tri-state buffer means is a final low-pass filtered feedback signal in the sequence of low-pass filtered feedback signals.

15. The digital filter bank device of claim 8, wherein each of the filter means includes first and second signal select means, pole signal processing means, parallel-to-serial conversion means, shift register means, first and second memory means, and zero signal processing means, wherein

the first signal select means includes a first input for receiving the filter input signal, a second input for receiving a first memory data output from the first memory means, and an output for selective transmission of the first memory data output as a first selected signal,

the pole signal processing means includes a first input for receiving the first selected signal and a second input for receiving a second selected output from the second signal select means, said pole signal processing means generating a pole signal for inclusion in the summations of product terms according to the distributed arithmetic algorithm;

the second signal select means has a first input for receiving the pole signal, a second input for receiving the first memory data output, and an output for transmission of the selected first memory data output as a second selected signal,

the parallel-to-serial conversion means has an input for receiving the pole signal, said parallel-to-serial conversion means converting the pole signal from a parallel format to a serial format including a plurality of bits of data,

the shift register means has an input for receiving the serial format pole signal and includes means for constructing first and second memory addresses using bits of data of the serial format pole signal,

the first memory means includes first addressing means for retrieving first digital filter characteristic coefficient data stored in the shift register means and for storing the retrieved first digital filter characteristic coefficient data as first memory data,

the second memory means includes second addressing means for retrieving second digital filter characteristic coefficient data stored in the shift register means and for storing the retrieved second digital filter characteristic coefficient data as second memory data, and

the zero signal processing means includes an input for receiving the second memory data, means for processing the second memory data as summations of product terms according to the distributed arithmetic algorithm, and means for transmitting the processed second memory data as the high-pass filtered signal and the low-pass filtered signal.

16. The digital filter bank device of claim 15, wherein the zero signal processing means includes means for transmitting the processed second memory data as the high-pass filtered signal, the low-pass filtered signal, and a band-pass filtered signal.

17. The digital filter bank device of claim 16, wherein the first signal select means includes first and second arrays of tri-state buffer means having respective first and second output lines, wherein the first and second output lines are tied to form a first select output, and wherein the first and second arrays of tri-state buffer means include respective first and second output enable inputs to independently control provision of the first selected signal to the first select output.

18. The digital filter bank device of claim 16, wherein the second signal select means includes first and second arrays of tri-state buffer means having respective first and second output lines, wherein the first and second output lines are tied to select output select output, and wherein the first and second arrays of tri-state buffer means include respective first and second output enable inputs to independently control provision of the second selected signal to the second select output.

19. The digital filter bank device of claim 16, wherein the pole signal processing means comprises an array of registers, an array of adders, a set of stage register arrays, and an array of AND-OR logic gates, wherein

the set of stage register arrays includes means for receiving the second selected signal and for latching the second selected signal for transmission to the array of AND-OR logic gates,

the array of AND-OR logic gates includes means for receiving the latched second selected signal, means for conditioning the latched second selected signal, and means for transmitting the conditioned second selected signal to the array of adders,

the array of adders includes means for receiving the conditioned second selected signal, means for receiving the first selected signal, and means for adding the conditioned second selected signal and the first selected signal to generate a selected signal sum for transmission to the array of registers, and

the array of registers includes means for receiving the selected signal sum and for latching the selected signal sum as the pole signal, according to a clock signal.

20. The digital filter bank device of claim 16, wherein the first memory means is a read-only memory.

21. The digital filter bank device of claim 16, wherein the second memory means is a read-only memory.

22. The digital filter bank device of claim 16, wherein the first memory means is a programmable array logic memory device.

23. The digital filter bank device of claim 16, wherein the second memory means is a programmable array logic memory device.

24. The digital filter bank device of claim 15, wherein the zero signal processing means includes an array of registers, an array of adders, a set of stage register arrays, and an array of AND-OR logic gates, wherein

the array of AND-OR logic gates including means for receiving a register output from the set of stage register arrays, means for conditioning the register output to produce a conditioned pole signal, and means for providing the conditioned pole signal to the array of adders,

the array of adders including means for receiving the conditioned pole signal and the second memory data, means for adding the conditioned pole signal and the second memory data to produce a summation, and means for providing the summation to the array of registers,

the array of registers including means for receiving and latching the summation and means for providing the summation to the set of stage register arrays according to a clock signal, and

the set of stage register arrays including means for receiving the latched summation and means for providing the latched summation to the frequency bank select means as the high-pass filtered signal and the low-pass filtered signal.

25. The digital filter bank device of claim 24, wherein the zero signaling processing means further includes means for providing the latched summation to the frequency bank select means as a band-pass filtered signal.

26. A method of filtering an external input signal to generate a filtered digital output signal, comprising the steps of:

a. choosing between the external input signal and a low-pass feedback signal to select a filter input;

b. filtering the filter input as a first summation of product terms according to a distributed arithmetic algorithm, to produce a high-pass filtered signal;

c. filtering the filter input as a second summation of product terms according to the distributed arithmetic algorithm and at a decimated sample rate, to produce a low-pass filtered signal;

d. performing a next selection of the filter input as in said step a, using the low-pass filtered signal as the low-pass feedback signal; and

e. transmitting the high-pass filtered signal as the filtered digital output signal.

27. The method of claim 26, wherein the steps b and c are performed by a filter bank which includes a plurality of filters organized as a plurality of banks of filters, wherein the plurality of filters generates a plurality of filtered outputs having a plurality of frequency bands, and wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

28. The method of claim 26, wherein the steps b and c are performed by a filter bank which includes a plurality of filters organized as a single bank of filters, wherein the plurality of filters generates a plurality of filtered outputs having a plurality of frequency bands, and wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

29. The method of claim 28, wherein the plurality of filters includes at least a high-pass filters for generating the high-pass filtered signal and a low-pass filters for generating the low-pass filtered signal.

30. The method of claim 29, wherein the steps b and c are performed simultaneously.

31. The method of claim 28,

wherein the plurality of filters includes at least a high-pass filters for generating the high-pass filtered signal, a low-pass filters for generating the low-pass filtered signal, and a plurality of band-pass filters for generating a respective plurality of band-pass filtered signals,

further including the step of choosing between the high-pass filtered signal and the band-pass filtered signal to select the filtered digital output signal.

32. The method of claim 31,

further comprising the step of filtering the filter input as a third summation of product terms according to a distributed arithmetic algorithm, to produce a band-pass filtered signal,

wherein the steps b and c and the step of filtering the filter input as a third summation of product terms all are performed simultaneously.

33. A method of operating a digital filter bank for filtering an external input signal to produce a filtered digital output signal, comprising the steps of:

a. storing an initial product term;

b. providing, the external input signal to a pole unit;

c. adding the external input signal to the initial product term to obtain a pole signal;

d. converting the pole signal to a sequence of serial bits to provide a serialized pole signal;

e. addressing a first memory location according to zeroth order term bits of the serialized pole signal;

f. addressing a second memory location according to zeroth order term bits of the serialized pole signal;

g. providing zeroth order term data corresponding to the first memory location to the pole unit;

h. providing zeroth order term data corresponding to the second memory location to a zero unit;

i. addressing a first memory location according to first order term bits of the serialized pole signal;

j. addressing a second memory location according to first order term bits of the serialized pole signal;

k. providing the first order term data corresponding to the first memory location to the pole unit;

l. dividing the zeroth order term data provided to the pole unit a designated number of times to obtain a division result and adding the division result to the first order term data provided to the pole unit, to obtain a new pole signal;

m. providing the first order term data corresponding to the second memory location to the zero unit;

n. dividing the zeroth order term data provided to the zero unit a designated number of times to obtain a division result and adding the division result to the first order term data provided to the zero unit to obtain filtered signal data;

o. adding the new pole signal to the filtered signal data; and

p. repeating the steps a through n until N-1 ordered terms have been produced and added, wherein N is a predetermined number.