Integrated circuit I/O using high performance bus interface

• US 5,841,715 A
• Filed: 02/10/1997
• Issued: 11/24/1998
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/796,782
• Time in Patent Office: 652 Days
• Field of Search: 365/203, 365/238.5, 365/235, 365/185.12, 365/233, 395/570
• US Class Current: 365/203
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Claims

1. A memory device comprising:

an array of memory cells for storing data, the memory array organized in rows and columns; and

a plurality of sense amplifiers coupled to the array of memory cells, the plurality of sense amplifiers for receiving and latching data for a row of the memory array;

synchronous bus interface circuitry having an input to receive an external clock signal, the synchronous bus interface circuitry for coupling to an external bus and to the plurality of sense amplifiers and configured to receive operation control information from the external bus in response to the external clock signal, the operation control information including first and second access mode control information, wherein the first access mode control information specifies whether the memory device operates in a page mode or normal mode of operation, and wherein the second access mode control information specifies whether the memory device precharges at least one of the columns of the memory array or saves data in the sense amplifiers after an access of the type specified in the first access mode control information.

2. The memory device of claim 1, wherein the memory device precharges at least one of the columns of the array of memory cells if data saved in the sense amplifiers is not accessed in a predetermined time after being saved in the sense amplifiers.

3. The memory device of claim 1, wherein the device comprises a dynamic random access memory (DRAM) device.

4. The memory device of claim 1, wherein the first and second access mode control information are included in a control field of a request packet carried on the external bus.

5. The memory device of claim 1, wherein the first and second access modes control information are independent from each other.

6. The memory device of claim 1, wherein the first access mode control information comprises a first signal, and the second access mode control information comprises a second independent signal.

7. The memory device of claim 1, wherein the memory array comprises at least two independent memory sections.

8. The memory device of claim 7, wherein the operation control information specifies one of the independent memory sections.

9. A method of accessing data stored in a memory device, the method comprising the steps of:

synchronously receiving first and second access mode control information from an external bus in response to an external clock signal;

sensing data from a row of the memory array in a page mode or a normal mode of operation in response to the receipt of the first access mode control information; and

subsequently precharging a plurality of columns in the memory array or saving sensed data from a selected row of memory cells in the memory array in response to the receipt of the second access mode control information.

10. The method of claim 9, wherein the first and second access mode control information are included in a control field of a request packet.

11. The method of claim 9, wherein the memory device comprises a dynamic random access memory (DRAM) device.