Method and system for controlling statistically multiplexed ATM bus

• US 5,841,774 A
• Filed: 07/16/1996
• Issued: 11/24/1998
• Est. Priority Date: 01/17/1994
• Status: Expired due to Term

• Current Assignee: Vringo Infrastructure, Inc. (XpresSpa Group, Inc. (f/k/a FORM Holdings Corp.))
• Original Assignee: Nokia Telecommunications Oy (Nokia Corporation)
• Inventors: Seppanen, Juha, Flinck, Hannu, Kaukanen, Osmo, Ylonen, Timo
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): YAO, KWANG BIN
• Application Number:
  US08/676,202
• Time in Patent Office: 861 Days
• Field of Search: 370/395, 370/400, 370/410, 370/401, 370/402, 370/403, 370/423, 370/438, 370/426, 370/439, 370/440, 370/451, 370/455, 370/461, 370/462, 370/398, 370/399, 395/200.01, 395/250, 395/280, 395/287, 395/288, 395/306, 395/307, 395/308, 395/427, 395/481, 395/485, 395/821, 395/842, 395/847, 395/848, 395/856, 395/860 , 395/200.74, 395/200.83, 364/239, 364/240, 364/240.2, 364/240.5, 364/242.6, 364/242.92, 364/240.3, 364/204.7, 364/937.01
• US Class Current: 370/399
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A method and system for controlling a statistically multiplexed ATM bus, to the bus being connected a bus controller and interface units for transmission of packets, i.e. cells, over the bus, in which, having detected, for each cell to be transmitted to an ATM bus, the address of the interface unit participating in the transmission, the bus controller sets the address on an address bus of the ATM bus, thereby activating transmission of the cell from the bus controller to the interface unit, or vice versa, over a data bus of the ATM bus. During the transmission of the cell, the bus controller fetches the next interface unit address for transmission of the next cell from or to the interface unit concerned.

Claims

1. A method for controlling a statistically multiplexed ATM bus in a system having a bus controller and a plurality of interface units having respective addresses, the interface units being connected to the bus controller by the bus, the bus controller including a memory for storing said addresses, and the bus including four separate functional parts each constituted by respectively physically separate wires or leads, including a control bus arranged for transmitting cell synchronization signals and bit synchronization signals from the bus controller to the interface units, an address bus for arranged identifying individual ones of said interface units at respective succeeding times, by writing respective addresses for said individual units from said memory onto said bus, a data bus arranged for transmitting ATM cells from the respective said interface units, one unit at a time, to said bus controller, by respective transmissions which are synchronized by said cell synchronization signals, which indicate the start of each new cell on said bus and for reception of ATM cells by respective ones of said interface units, and a request-to-send lead arranged for transmitting a respective a request-to-send message from each said interface unit, to said bus controller,

said method comprising the steps of:

(a) maintaining said addresses in said memory in a predetermined order;

(b) writing said addresses from said memory onto said address bus in said predetermined order;

(c) each said interface unit, when having at least one ATM cell to be transmitted, upon detecting its own address from said address bus as a result of step (b) being conducted, transmitting a respective request-to-send signal on said request-to-send lead, to said bus controller;

(d) said bus controller detecting each said request-to-send signal, from said request-to-send lead, and, in response to receiving each said request-to-send signal, temporarily maintaining the respective said address on said address bus;

(e) said bus controller transmitting said synchronization signals on said control bus, each occurrence of temporarily maintaining of step (d) being ended by detection of rising edge of a respective next one of said synchronization signals by said bus controller;

(f) each said interface unit, in response to receiving a rising edge of a respective next cell synchronization signal on said control bus while its respective said address is being maintained on said address bus as a consequence of step (d) being conducted, transmitting the respective said at least one ATM cell on said data bus; and

(g) each time step (f) is being conducted, said bus controller conducting step (b) in respect to a respective next address in said predetermined order.

2. The method of claim 1, further comprising:

(h) for transmitting multiplexed ATM cells having respective address fields, from said bus controller to respective ones of said interface units, said bus controller reading identifiers of respective ones of said interface units from respective ones of said address fields; and

(i) both placing each of said identifiers in succession on said address bus and placing each respective cell being transmitted thereby in respective succession on said data bus; and

(j) as a consequence of step (I) being conducted, each of said interface units receiving only respective ones of said ATM cells transmitted by said bus controller.

3. The method of claim 1, wherein:

as a result of conducting step (e) synchronization signals being transmitted on said control bus as a succession of pulses having respective intervals between them; and

further including;

proportioning address space of said memory, access rate to said memory and cell transmission frequency on said data bus, so as to cause said bus controller to write successive ones of said addresses onto said address bus in step (b) in respective successive ones of said intervals.

4. The method of claim 1, wherein:

said interface units, among them, have at least two different ATM cell transmitting rates; and

as part of conducting step (a), said memory is provided with a respective number of memory locations for each of said interface units which is proportionate to the respective ones of said rates.

5. The method of claim 1, wherein:

said interface units, among them, have at least two different priority levels; and

as part of conducting step (a) said memory is provided with a respective number of memory locations for each of said interface units which is proportionate to the respective said levels of priority.

6. A system comprising:

a bus controller and a plurality of interface units having respective addresses, the interface units being connected to the bus controller by the bus, the bus controller including a memory for storing said addresses, and the bus including four separate functional parts each constituted by respectively physically separate wires or leads, including a control bus arranged for transmitting cell synchronization signals and bit synchronization signals from the bus controller to the interface units, an address bus for arranged identifying individual ones of said interface units at respective succeeding times, by writing respective addresses for said individual units from said memory onto said bus, a data bus arranged for transmitting ATM cells from the respective said interface units, one unit at a time, to said bus controller, by respective transmissions which are synchronized by said cell synchronization signals, which indicate the start of each new cell on said bus and for reception of ATM cells by respective ones of said interface units, and a request-to-send lead arranged for transmitting a respective a request-to-send message from each said interface unit, to said bus controller;

said memory being arranged to maintain maintaining said addresses in said memory in a predetermined order;

said bus controller being arranged to write said addresses from said memory onto said address bus in said predetermined order;

each said interface unit being arranged such that, when having at least one ATM cell to be transmitted, upon detecting its own address from said address bus as a result of that address being written onto said address bus by said bus controller, said interface unit transmits a respective request-to-send signal on said request-to-send lead, to said bus controller;

said bus controller being arranged to detect each said request-to-send signal, from said request-to-send lead, and, in response to receiving each said request-to-send signal, to temporarily maintain the respective said address on said address bus;

said bus controller being arranged to transmit said synchronization signal on said control bus;

each said interface unit, in response to receiving a rising edge of respective next cell synchronization signal on said control bus while its respective said address is being maintained on said address bus, being arranged to transmit the respective said at least one ATM cell on said data bus.

7. The system of claim 6, further comprising:

for transmitting multiplexed ATM cells from having respective address fields, from said bus controller to respective ones of said interface units, said bus controller being arranged to read identifiers of respective ones of said interface units from respective ones of said address fields; and

said bus controller being arranged to place each of said identifiers in succession on said address bus and to place each respective cell being transmitted thereby, in respective succession on said data bus; and

each of said interface units being arranged to receive only respective ones of said ATM cells transmitted by said bus controller.

8. The system of claim 6, wherein:

said bus controller is arranged to transmit said synchronization signals on said control bus as a succession of pulses having respective intervals between them; and

said bus controller has an address space of said memory, access rate to said memory and cell transmission frequency on said data bus, such as to cause said bus controller to write successive ones of said addressed onto said address bus in respective successive ones of said intervals.

9. The system of claim 6, wherein:

said interface units, among them, have at least two different ATM cell transmitting rates; and

said memory is provided with a respective number of memory locations for each of said interface units which is proportionate the respective ones of said rates.

10. The system of claim 6, wherein:

said interface units, among them, have at least two different priority levels; and

said memory is provided with a respective number of memory locations for each of said interface units which is proportionate to the levels of priority.

11. A system for controlling a statistically multiplexed ATM bus, comprising:

an ATM bus having an address bus and a data bus;

a bus controller arranged for transmitting cells over said ATM bus;

a plurality of interface units connected to the controller by said ATM bus;

said bus controller being provided with a memory in which are stored addresses of said interface units such that, for each cell to be transmitted to said ATM bus by a respective said interface unit, the address of the respective said interface unit participating in the transmission can be read from the memory and set on said address bus of said ATM bus;

said bus controller being arranged to transmit ATM cells over said data bus of said ATM bus from said bus controller to only its respective ones of interface units and vice versa at such a rate that during the transmission of each such cell, said bus controller can fetch a respective next interface unit address for transmission of respective next such cell to said data bus; and

said ATM bus further including a synchronization bus for transmitting cell sync pulses from said bus controller;

said bus controller having an address space for said memory a memory access rate, and said data bus having transmission frequency, which are proportioned to one another such that all of said address space is arranged to be scanned between each two successive ones of said cell sync pulses by conducting a poll that covers the addresses of all of said interface units.