Spread spectrum chip rate tracking system

• US 5,841,808 A
• Filed: 03/23/1995
• Issued: 11/24/1998
• Est. Priority Date: 03/23/1995
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Mcdonnell Douglas Corporation (The Boeing Co.)
• Inventors: Rizzo, Michael A., Gorney, Robert E.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/409,763
• Time in Patent Office: 1,342 Days
• Field of Search: 375/200, 375/206, 375/208-210, 375/367, 370/18, 370/107, 370/515
• US Class Current: 375/150
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop

Abstract

In a new receiver design, the specific transmitter unit is unchanged from a prior patent application but may also be substantially as described in the prior art. The transmitter is initially activated by the input of the pseudo-random generator code. This code may be any alpha-numeric series, but must be identical to that input to the receiver. When the code is input through the keypad, the transmitter uses internal algorithms to generate a unique shift-register feedback combination. This creates a pseudo-random (PN) code which repeats after a programmable number of bits, depending upon desired maximal signal correlation time. That is the longer the code the longer the correlation time. This PN code sequence is clocked at the desired clock (CHIP) rate inside the transmitter unit. The PN code sequence which is thus generated is then added in phase to the data which is a substantially lower rate than the CHIP rate. After mixing with the PN code and data, the RF frequency CW signal power is spread across a frequency band equivalent to twice the PN code clock rate. The signal power density per hertz is now well below an identical non-spread signal at the communications data rate and ideally below the systems noise level. At the receiver the same pseudo-random code which was used to transmit the information is entered into the receiver unit for activation. This is then used to configure three programmable PN sequence generators which output three identical PN code sequences which vary only in a one-half phase shift of the CHIP rate from each other. The signals received by the antenna are converted to an intermediate frequency and mixed with the locally generated PN code sequences. When code alignment occurs, threshold detector circuitry senses the presence of the correlated data signals. The relative level of the signals are then sensed by the microprocessor which varies the PN clock oscillator to maintain lock with the incoming signal. The data is now available as useable information at the data port.

Claims

1. A spread spectrum communications system having a transmitter for transmitting a spread spectrum signal containing data and a digital code and a receiver for receiving the spread spectrum signal and for demodulating the spread spectrum signal with the same digital code, the improvement in said receiver comprising:

a. means for selecting a base digital code identical to the digital code used by the transmitter,

b. means for generating a leading digital code identical to the base digital code and leading the base digital code by a fixed phase shift,

c. means for generating a lagging digital code identical to the base digital code and lagging the base digital code by the fixed phase shift,

d. means for individually mixing the leading digital code, the base digital code, and the lagging digital code with the spread spectrum signal to thereby generate a leading information signal, a base information signal and a lagging information signal, respectively,

e. means for comparing relative power levels of the leading information signal and the lagging information signal,

f. feedback means for altering the rate at which the leading digital code, the base digital code and the lagging digital code are clocked based upon the relative power levels of the leading information signal and the lagging information signal until the respective power levels of the leading information signal and the lagging information signal are equal, and

g. means for out-putting the base information signal once the respective power levels of the leading information signal and the lagging information signal are equal to thereby maximize the base information signal.

2. A spread spectrum communications system as described in claim 1 wherein said fixed phase shift introduced by said means for generating the leading digital code and said means for generating the lagging digital code is equal to one half cycle.

3. A spread spectrum communications system according to claim 1 wherein said means for selecting the base digital code selects a pseudo random code.

4. A spread spectrum communications system according to claim 1 wherein said means for generating the leading digital code and said means for generating the lagging digital code both clock the respective digital code at a predetermined chip rate.

5. A spread spectrum communications system according to claim 1 wherein said comparing means determines a difference between the relative power levels of the leading information signal and the lagging information signal.

6. A spread spectrum communications system according to claim 1 wherein said feedback means alters the rate at which the leading digital code, the base digital code and the lagging digital code are clocked in proportion to the difference between the relative power levels of the leading information signal and the lagging information signal.

7. A receiving system for receiving transmitted information including a transmitted PN code, the receiving system comprising:

a. a receiving antenna for intercepting a transmitted radio frequency signal,

b. a first mixer coupled to said antenna for mixing the intercepted signal with a locally derived oscillator signal tuned below the RF carrier of the transmitted frequency to generate an intermediate frequency signal,

c. first means for generating a first digital PN Code sequence identical to the transmitted PN Code, said first generating means coupled to a clock generator for clocking said first digital PN Code sequence,

d. first mixing means for mixing said first digital PN Code sequence with said intermediate frequency signal and generating a first output signal,

e. first correlating means for correlating said first output signal and generating a first correlated signal,

f. second means for generating a second digital PN Code sequence identical to the transmitted PN Code and leading said first digital PN Code sequence by a fixed phase shift, said second generating means coupled to the clock generator for clocking said second digital PN Code sequence,

g. second mixing means for mixing said second digital PN Code sequence with said intermediate frequency signal and generating a second output signal,

h. second correlating means for correlating said second output signal and generating a second correlated signal,

i. third means for generating a third digital PN Code sequence identical to the transmitted PN Code and lagging said first digital PN Code sequence by the fixed phase shift, said third generating means coupled to the clock generator for clocking said third digital PN Code sequence,

j. third mixing means for mixing said third digital PN Code sequence with said intermediate frequency signal and generating a third output signal,

k. third correlating means for correlating said third output signal and generating a third correlated signal,

l. threshold detecting means for detecting the energy of said second and third correlated signals,

m. a phase locked loop coupled to said first correlating means for sensing the first correlated signal and for changing frequency to lock to the first correlated signal,

n. a demodulator coupled to the phase locked loop for demodulating data from the first correlated signal,

o. a microprocessing means for comparing the energy of said second and third correlated signals and generating a digital representation of the difference, said microprocessing means providing a digital command to said clock generator to alter the clock rate until said difference is zero, said microprocessing means also receiving the data from said demodulator and outputting said data to a data port, and

p. means, responsive to said first mixing means, for band pass filtering said first output signal, said band pass filtering means centered at a carrier frequency.

8. A receiving system as described in claim 7 wherein said first, second and third correlating means include a chip rate retard/delay circuit.

9. A receiving system as described in claim 7 wherein said first, second and third digital PN Code generating means each comprise:

a. a programmable shift register adapted to receive a configuration signal and clocked by said clock generator, said programmable shift register outputting register information to a plurality of clocked multiplexers, wherein at least one of said multiplexers and said programmable shift register output a signal to a first exclusive OR gate, and

b. a second exclusive OR gate for receiving the output from said first exclusive OR sate and the output of at least one other multiplexer and for providing an output which comprises the PN code to said programmable shift register.

10. A communications method comprising the steps of:

transmitting a spread spectrum signal containing data and a digital code;

receiving the spread spectrum signal; and

demodulating the spread spectrum signal with the same digital code, said demodulating step comprising the steps of;

generating a base digital code identical to the digital code of the transmitted spread spectrum signal;

generating a leading digital code identical to the base digital code and leading the base digital code by a fixed phase shift,

generating a lagging digital code identical to the base digital code and lagging the base digital code by the fixed phase shift,

individually mixing the leading digital code, the base digital code, and the lagging digital code with the spread spectrum signal to thereby generate a leading information signal, a base information signal and a lagging information signal, respectively,

comparing relative power levels of the leading information signal and the lagging information signal,

altering the rate at which the leading digital code, the base digital code and the lagging digital code are clocked based upon the relative power levels of the leading information signal and the lagging information signal until the respective power levels of the leading information signal and the lagging information signal are equal, and

outputting the base information signal once the respective power levels of the leading information signal and the lagging information signal are equal to thereby maximize the base information signal.

11. A communications method according to claim 10 wherein the fixed phase shift generated by said steps of generating the leading digital code and the lagging digital code each comprises one half cycle.

12. A communications method according to claim 10 wherein said steps of generating the leading digital code and the lagging digital code each comprise a step of clocking the respective digital code at a predetermined chip rate.

13. A communications method according to claim 10 wherein said comparing step comprises a step of determining a difference between the relative power levels of the leading information signal and the lagging information signal.

14. A communications method according to claim 13 wherein said altering step comprises a step of altering the rate at which the leading digital code, the base digital code and the lagging digital code are clocked in proportion to the difference between the relative power levels of the leading information signal and the lagging information signal.