Method and apparatus for design verification using emulation and simulation

• US 5,841,967 A
• Filed: 10/17/1996
• Issued: 11/24/1998
• Est. Priority Date: 10/17/1996
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Bershteyn, Mikhail, Sample, Stephen P.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Baderman, Scott T.
• Application Number:
  US08/733,352
• Time in Patent Office: 768 Days
• Field of Search: 395/183.09, 395/183.04, 395/183.13, 395/500, 395/183.05, 364/232.3, 364/933.8, 364/488, 364/489, 364/578, 371/27.4
• US Class Current: 714/33
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

Claims

1. An apparatus for design verification using emulation and simulation comprising:

at least one reconfigurable element for emulating a first portion of a design;

at least one microprocessor for simulating a second portion of said design, connected to said reconfigurable element so as to minimize time for transferring data between said first portion of said design and said second portion of said design; and

an event detector connected to said at least one microprocessor for detecting a plurality of events during design verification, relieving said at least one microprocessor from performing event detection.

2. The apparatus of claim 1 further comprising a scheduler for scheduling operations that said at least one microprocessor would ordinarily schedule.

3. The apparatus of claim 1 further comprising a second microprocessor.

4. The apparatus of claim 3 further comprising a selector for selecting independent fragments of said second portion of said design for parallel execution by each of said microprocessors.

5. The apparatus of claim 1 further comprising a selector for selecting independent fragments of said second portion of said design for execution by said microprocessor.

6. The apparatus of claim 1 wherein said at least one reconfigurable element further comprises a reconfigurable interconnect component.

7. The apparatus of claim 1 wherein said at least one reconfigurable element further comprises a reconfigurable logic component.

8. The apparatus of claim 6 wherein said at least one reconfigurable element comprises a plurality of reconfigurable logic components, and said reconfigurable interconnect component interconnects said plurality of reconfigurable logic components.

9. The apparatus of claim 1 further comprising a memory connected to said at least one microprocessor.

10. The apparatus of claim 1 further comprising a bus controller connected to said at least one microprocessor.

11. The apparatus of claim 1 wherein said second portion of said design is described in a behavioral language.

12. The apparatus of claim 1 further comprising a second reconfigurable element.

13. The apparatus of claim 12 wherein said second reconfigurable element further comprises a scheduler for scheduling fragments of said second portion of said design to be simulated by said at least one microprocessor upon detection of events by said event detector.

14. The apparatus of claim 12 wherein said second reconfigurable element further comprises a selector for selecting independent fragments of said second portion of said design for execution by said at least one microprocessor.

15. The apparatus of claim 12 wherein said second reconfigurable element further comprises a detector for detecting said plurality of events during design verification, relieving said at least one microprocessor from performing said event detection.

16. The apparatus of claim 12 further comprising an interconnect element connecting said at least one reconfigurable element and said second reconfigurable element.

17. The apparatus of claim 1 further comprising a reconfigurable interconnect element connecting said at least one reconfigurable element and said at least one microprocessor.

18. The apparatus of claim 10 further comprising a system controller connected to said bus controller through a system bus.

19. The apparatus of claim 1 further comprising a global bus connected to said at least one microprocessor.

20. The apparatus of claim 19 wherein said global bus further comprises a plurality of signals connected in parallel to said at least one microprocessor.

21. The apparatus of claim 19 wherein said global bus further comprises a second line serially connecting said at least one microprocessor.

22. The apparatus of claim 19 wherein said global bus connects at least one signal between said at least one reconfigurable element and said at least one microprocessor.

23. An apparatus for emulation and simulation comprising:

a plurality of simulation modules, each having a microprocessor for simulating a design;

a first reconfigurable element for emulating said design, connected to said simulation modules;

said plurality of simulation modules further comprising a second reconfigurable element; and

said second reconfigurable element comprising an event detector for detecting events to assist said microprocessors in simulating said design.

24. The apparatus of claim 23 wherein at least one of said simulation modules transmits a data value to said first reconfigurable element.

25. The apparatus of claim 23 wherein at least one of said simulation modules transmits a data value outside of said simulation module.

26. The apparatus of claim 23 wherein one of said microprocessors transmits a data value to said second reconfigurable element.

27. The apparatus of claim 23 wherein said second reconfigurable element comprises a decoder to decode a signal received from one of said microprocessors.

28. The apparatus of claim 27 wherein said second reconfigurable element further comprises a selector that is enabled when said decoder recognizes said signal from one of said microprocessors.

29. The apparatus of claim 28 wherein said second reconfigurable element further comprises a register for capturing said signal, wherein said register is enabled by said selector.

30. The apparatus of claim 23 wherein at least one of said plurality of simulation modules receives a data signal from a second of said plurality of simulation modules.

31. The apparatus of claim 23 wherein at least one of said plurality of simulation modules receives a data signal from said first reconfigurable element.

32. The apparatus of claim 23 wherein one of said microprocessors receives a data signal from said second reconfigurable element.

33. The apparatus of claim 23 wherein said second reconfigurable element further comprises a decoder for recognizing a microprocessor signal indicating one of said microprocessors is ready to capture a data value from said second reconfigurable element.

34. The apparatus of claim 23 wherein said second reconfigurable element further comprises a multiplexer that selects a data value for capture by one of said plurality of microprocessors.

35. The apparatus of claim 23 wherein said event detector causes an interrupt to one of said plurality of microprocessors when an event is detected.

36. The apparatus of claim 23 further comprising a plurality of event detector groups that process a plurality of events.

37. The apparatus of claim 36 wherein said plurality of event detector groups comprise at least one event detector.

38. The apparatus of claim 36 wherein said plurality of event detector groups further comprise at least one AND gate.

39. The apparatus of claim 36 wherein said plurality of event detector groups process a first event before a second event.

40. The apparatus of claim 36 wherein said plurality of eve nt detectors detect a first event and a second event and process said first event prior to said second event.

41. The apparatus of claim 40 wherein said plurality of event detectors create a first busy signal representing said first event and a second busy signal representing said second event.

42. The apparatus of claim 36 wherein said plurality of event detector groups detect a first busy signal and a second busy signal, and process said second busy signal when said first busy signal is not asserted.

43. The apparatus of claim 42 wherein each of said first busy signal and said second busy signal are individually formed with an OR gate connected to at least one of said plurality of event detectors.

44. The apparatus of claim 42 wherein each of said firs t busy signal and said second busy signal are individually formed with a wired OR connected to at least one of said plurality of event detectors.

45. The apparatus of claim 23 wherein a global bus connects said plurality of simulation modules.

46. The apparatus of claim 42 further comprising a global bus that transmits said first busy signal and said second busy signal to said plurality of simulation modules.

47. The apparatus of claim 36 wherein said plurality of event detectors detect a plurality of event types.

48. The apparatus of claim 47 wherein said simulation modules further comprise a simulation advancement circuit that produces a time advance signal when said plurality of event types are not detected by said plurality of event detectors.

49. The apparatus of claim 48 wherein said simulation advancement circuit comprises a counter and a NOR gate.

50. The apparatus of claim 48 further comprising a global bus that transmits said time advance signal.

51. The apparatus of claim 23 wherein said plurality of simulation modules are connected by a multiplexed bus.

52. The apparatus of claim 51 where in said multiplexed bus transfers said events between said plurality of simulation modules.

53. The apparatus of claim 51 wherein said plurality of simulation modules further comprise a transmit controller for controlling said multiplexed bus.

54. The apparatus of claim 50 wherein said global bus transmits said events between said plurality of simulation modules.

55. The apparatus of claim 23 wherein said first reconfigurable element comprises a first flip/flop.

56. The apparatus of claim 55 further comprising a second flip/flop placed downstream from said first flip/flop in order to eliminate a hold-time violation.

57. The apparatus of claim 23 wherein said first reconfigurable element comprises a clock circuit.

58. The apparatus of claim 57 wherein said clock circuit comprises a flip/flop.

59. The apparatus of claim 58 wherein said clock circuit is duplicated in said first reconfigurable element.

60. A method for simulating and emulating a design comprising the following steps:

importing said design, where a portion of said design is a behavioral design, to create a behavioral database;

dividing said behavioral design into a plurality of behavioral fragments;

preprocessing said behavioral database to form a preprocessed behavioral database;

generating a plurality of executables for a plurality of simulation modules for processing therein;

creating a netlist; and

processing said netlist to create configuration data for a plurality of reconfigurable elements.

61. The method in claim 60 wherein said preprocessing step further comprises the following steps:

partitioning said behavioral database into a plurality of clusters; and

transforming said design to eliminate a hold-time violation.

62. The method of claim 60 wherein said processing step further includes the following steps:

partitioning said netlist creating a partitioned netlist;

placing said partitioned netlist; and

routing said partitioned netlist.

63. A method for combining emulation and simulation comprising the following steps:

connecting an emulator and a plurality of microprocessors so as to minimize time for transferring data between said emulator and said microprocessors;

emulating a first portion of a design by said emulator;

simulating a second portion of said design by said simulator; and

detecting a plurality of events by said emulator that would ordinarily be detected by said microprocessors.

64. The method of claim 63 further comprising the step of scheduling a plurality of operations by said emulator that would ordinarily be scheduled by said microprocessors.

65. The method of claim 63 further comprising:

selecting a plurality of independent fragments of said second portion of said design; and

executing said plurality of independent fragments in parallel by said microprocessors.

66. The method of claim 63 wherein said simulating step further comprises the step of simulating said first portion of said design described in a behavioral language.

67. The method of claim 63 further comprising the step of manipulating said plurality of events by said emulator that would ordinarily be manipulated by said microprocessors.

68. The method of claim 63 further comprising the step of eliminating a plurality of hold-time violations.

69. The method of claim 63 wherein said first portion of said design overlaps with said second portion of said design.

70. The method of claim 63 wherein said first portion of said design is the same as said second portion of said design.