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Method and apparatus for design verification using emulation and simulation

  • US 5,841,967 A
  • Filed: 10/17/1996
  • Issued: 11/24/1998
  • Est. Priority Date: 10/17/1996
  • Status: Expired due to Term
First Claim
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1. An apparatus for design verification using emulation and simulation comprising:

  • at least one reconfigurable element for emulating a first portion of a design;

    at least one microprocessor for simulating a second portion of said design, connected to said reconfigurable element so as to minimize time for transferring data between said first portion of said design and said second portion of said design; and

    an event detector connected to said at least one microprocessor for detecting a plurality of events during design verification, relieving said at least one microprocessor from performing event detection.

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