Single bus architecture supporting subsystems of various criticality levels

• US 5,841,969 A
• Filed: 08/13/1996
• Issued: 11/24/1998
• Est. Priority Date: 08/13/1996
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Fye, James C.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US08/696,419
• Time in Patent Office: 833 Days
• Field of Search: 395/185.01, 395/185.07, 395/185.02, 395/185.05, 395/185.08, 395/182.22, 395/182.21, 395/185.09, 395/500, 371/67.1, 371/68.1
• US Class Current: 714/56
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites

Abstract

Communications systems architecture using a single shared resource bus to interconnect a plurality of subsystems each handling information having a first predetermined importance level and an error detect wrapper for encoding information to and from each such subsystem to detect errors in transmission along the shared resource bus. A heartbeat monitor is also provided for use in those subsystems handling information having a second predetermined level of importance to disable the subsystem if an error occurs within the subsystem.

Claims

1. An architecture for use with interconnecting a plurality of avionics subsystems of an overall system, each subsystem operating on information useful in the overall system which information may be of various levels of importance to the overall system, each subsystem having a bus bridge operable to conduct input and output information to and from its subsystem, comprising:

a single shared resource bus connected to each of the bus bridges; and

an error detect wrapper connected to those bus bridges associated with subsystems operating on information having at least a first predetermined level of importance to the overall system, said error detect wrapper encoding information being sent from a subsystem to the shared resource bus and checking the coding of information received from the shared resource bus to detect if there has been any transmission error between a sending subsystem and a receiving subsystem.

2. Apparatus according to claim 1 further including a processor associated with a subsystem for processing information to and from one or more of the subsystems and further including means connected between each error detect wrapper and the processor to inform the processor of a transmission error when it occurs.

3. Apparatus according to claim 1 further including a heartbeat monitor in each subsystem operating on information having at least a second predetermined level of importance, said heartbeat monitor operating to produce a fault signal upon the occurrence of an error within the subsystem.

4. Apparatus according to claim 3 further including means to disable any subsystem having a heartbeat monitor producing a fault signal.

5. Apparatus according to claim 1 wherein each subsystem includes resources apparatus to receive information from remote sources and to characterize such information for use in the subsystem.

6. Apparatus according to claim 5 further including a heartbeat monitor connected to the resources apparatus in each subsystem operating on information having at least a second predetermined level of importance, said heartbeat monitor operating to produce a fault signal upon the occurrence of an error in the subsystem.

7. Apparatus according to claim 1 further including control means operable to enable and disable the error detect wrapper to a predetermined desired extent.

8. Apparatus according to claim 7 where the control means enables and disables the error detect wrapper to the desired extent in accordance with the level of importance of the information.