System and method of processing instructions for a processor

• US 5,841,998 A
• Filed: 05/09/1997
• Issued: 11/24/1998
• Est. Priority Date: 12/31/1996
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: Metaflow Technologies, Inc. (STMicroelectronics NV)
• Inventors: Isaman, David L.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/853,566
• Time in Patent Office: 564 Days
• Field of Search: 395/384, 395/385, 395/386, 395/387, 395/388, 395/389
• US Class Current: 712/208
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system includes an instruction unit generating a program instruction. A parse unit coupled to the instruction unit receives the program instruction. The parse unit determines whether the instruction contains both load and store operations and generates first and second parcels for the instruction containing both load and store operations. A decode unit coupled to the parse unit receives the first and second parcels. The decode unit attaches an identification number to the first and second parcels, the identification number of the second parcel being determinable from the identification number of the first parcel. An issue unit coupled to the decode unit receives the first and second parcels. The issue unit issues the parcels to an instruction shelf, a load shelf, and a store shelf for instruction execution.

Claims

1. A data processing system comprising:

an instruction unit generating a program instruction;

a parse unit coupled to the instruction unit and receiving the program instruction, the parse unit determining whether the instruction requires both load and store operations and generating only first and second parcels for the instruction containing both load and store operations;

a decode unit coupled to the parse unit and receiving the first and second parcels, the decode unit attaching a different identification number to the first and second parcels, the identification number of the second parcel being determinable from the identification number of the first parcel; and

an issue unit coupled to the decode unit and receiving the first and second parcels and issuing the first and second parcels.

2. The data processing system according to claim 1, wherein the parse unit includes:

an instruction parser connected to the instruction unit and receiving the program instruction;

a decoder connected to the instruction parser; and

a parse control unit connected to the instruction parser and the decoder, the parse control unit controlling operation of the parse unit.

3. The data processing system according to claim 1, wherein the decode unit includes:

decode registers receiving the first and second parcels from the parse unit;

identification number generator connected to the decode registers and generating the identification number for the first and second parcels;

scoreboard unit connected to the decode registers and the identification number generator, the scoreboard unit including a locker identification number of a data to be stored in a memory; and

control logic unit connected to the decode registers, the identification number generator and the scoreboard unit, the control logic unit controlling operation of the decode unit.

4. The data processing system according to claim 3, wherein the control logic unit includes:

a decoder receiving one of the first and second parcels and outputting a load enable signal and a store enable signal when the one of the first and second parcels contains load and store operations;

a first logic unit coupled to the load and store enable signals;

a second logic unit coupled to the load enable signal and a signal informing valid parcel and empty issue register available, the second logic unit outputting whether a destination register is valid;

an adder coupled to the identification number from the identification number generator and outputting the identification number plus a constant number; and

a multiplexer receiving an output of the adder and a locker identification number, and outputting a signal according to an output from the first logic unit.

5. The data processing system according to claim 1, wherein the issue unit issues the first and second parcels to an instruction shelf, a load shelf, and a store shelf for instruction execution.

6. The data processing system according to claim 5, wherein the issue unit includes:

issue registers receiving the first and second parcels from the decode unit; and

control logic units connected to the issue registers, the instruction shelf, the load shelf, and the store shelf, the control logic units controlling a copying of the first and second parcels to appropriate ones of the instruction shelf, the load shelf, and the store shelf.

7. The data processing system according to claim 1, wherein the load and store operations concern a same address location in a memory and the address is calculated only once for the program instruction.

8. The data processing system according to claim 1, further comprising an execution unit including one address calculating unit requiring only one address calculating cycle for the program instruction.

9. The data processing system according to claim 1, wherein the execution unit includes:

the instruction shelf outputting a valid signal line for executing the instruction, a load enable signal, and a store enable signal;

the load shelf connected to the instruction shelf;

the store shelf connected to the instruction shelf;

an arithmetic logic unit connected to the instruction shelf; and

a logic unit receiving the valid signal line, the load enable signal, and the store enable signal from the instruction shelf, the logic unit outputting first and second control signals to the load shelf and store shelf, respectively.

10. A method for processing data comprising the steps of:

parsing an instruction containing both load and store operations to generate only first and second parcels;

decoding the first and second parcels;

issuing the first and second parcels; and

executing the first and second parcels.

11. The method for processing data according to claim 10, wherein the load and store operations are performed in only one of the first and second parcels.

12. The method for processing data according to claim 10, wherein the load and store operations have the same address location in memory and the address location is calculated only once for both the load and store operations.

13. The method for processing data according to claim 10, wherein the step of decoding the first and second parcels includes the step of generating both a load enable signal and a store enable signal for a same parcel.

14. The method for processing data according to claim 12, wherein the step of decoding the first and second parcels includes the step of generating a locker identification number of a source data to be stored in a memory as an identification number of the first parcel having the load and store operations plus a constant number.

15. The method for processing data according to claim 10, wherein the step of issuing the first and second parcels places one of the first and second parcels on both a load shelf and a store shelf.

16. The method for processing data according to claim 10, wherein the step of executing the first and second parcels consumes only one address calculation cycle for the instruction.

17. The method for processing data according to claim 10, further comprising the step of retiring the first and second parcels.

18. A method for processing data comprising the steps of:

parsing an instruction containing both load and store operations to generate only first and second parcels;

decoding the first and second parcels, the step of decoding the first and second parcels including the step of generating both a load enable signal and a store enable signal for a same parcel;

issuing the first and second parcels and placing one of the first and second parcels on both a load shelf and a store shelf; and

executing the first and second parcels.

19. The method for processing data according to claim 18, wherein the load and store operations have the same address location in memory and the address location is calculated only once for both the load and store operations.

20. The method for processing data according to claim 18, wherein the step of decoding the first and second parcels includes the step of generating a locker identification number of a source data to be stored in a memory as an identification number of the first parcel having the load and store operations plus a constant number.

21. The method for processing data according to claim 18, wherein the step of executing the first and second parcels consumes only one address calculation cycle for the instruction.

22. The method for processing data according to claim 18, further comprising the step of retiring the first and second parcels.

23. The method for processing data according to claim 18, wherein the instruction containing both the load and store operations also contains an additional operation, the first parcel containing the load and store operations and the second parcel containing the additional operation.