Information handling system having a register remap structure using a content addressable table

• US 5,841,999 A
• Filed: 04/17/1996
• Issued: 11/24/1998
• Est. Priority Date: 04/17/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Le, Hung Qui, Hokenek, Erdem
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/633,327
• Time in Patent Office: 951 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/393, 395/394, 395/392, 395/800.41, 395/800.42, 395/800.33, 395/800.23
• US Class Current: 712/217
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

An information handling system includes an instruction unit, one or more execution units, a memory management unit, connected to the instruction unit, to a memory system, a cache management unit, one or more levels of cache memory associated with the one or more execution units, one or more I/O controllers connected to a bus which connects to the execution units and to the memory systems and to cache, and a completion unit for tracking sequence of instruction dispatch and instruction completion. The completion unit includes a Content Addressable Register Buffer Assignment Table, a Register Status Table, an Instruction Queue, and a Completion Table to control order of execution and completion of instructions in a sequence dependent on availability of operands.

Claims

1. An information handling system, comprising:

an instruction unit;

one or more execution units;

a memory management unit, connected to the instruction unit, and to a memory system;

one or more levels of cache memory associated with the one or more execution units;

a system bus connected to the execution units and to the memory system and to the cache memory;

one or more I/O controllers connected to the system bus for controlling I/O devices; and

a completion unit for tracking sequence of instruction dispatch and instruction completion, wherein speculatively assigned registers are released as soon as a branch instruction is found to be mispredicted.

2. An information handling system, according to claim 1, wherein the completion unit comprises:

a content addressable register buffer assignment table;

a register status table;

an instruction queue; and

a completion table to control order of execution and completion of instructions in a sequence dependent on availability of operands.

3. An information handling system according to claim 2, further comprising one or more register units, for temporary storage of information related to instruction execution.

4. An information handling system according to claim 3, wherein the one or more register units further comprise:

a first set of predefined registers; and

a first set of buffer registers.

5. An information handling system according to claim 3, wherein the one or more register units further comprise:

a second set of predefined registers; and

a second set of buffer registers.

6. An information handling system according to claim 4, wherein the first set of predefined registers further comprises:

a first number of architected general purpose registers; and

the first set of buffer registers comprises a second number of registers assignable to supplement the architected general purpose registers.

7. A method for controlling completion of instructions executed in a random sequence, comprising the steps of:

storing a tag, associated with an instruction, in a completion table, indicating a position of the instruction in a sequence of completion of the instruction relative to other instructions;

associatively comparing source address pointers with entries in a content addressable buffer assignment table to identify a register to be used in execution of an instruction;

associatively comparing destination address pointers with entries in the content addressable buffer assignment table to reset indicators of register assignment;

assigning a buffer address pointer to the destination address pointer;

storing the assigned buffer address pointer in the content addressable buffer assignment table;

storing each destination address pointer and each assigned buffer address pointer in an instruction queue;

accessing an first operand for execution of an instruction by using the assigned buffer address pointer to address a buffer containing the first operand;

executing an instruction when all operands required for execution of the instruction are available;

reading the destination address pointer and the assigned buffer address pointer from the content addressable buffer assignment table;

gating completed instruction data from the assigned buffer to a general purpose register associated with the destination address;

gating results of completed instructions from the general purpose registers in a predetermined sequence determined by the tags stored in the completion table.

8. A method according to claim 7, further comprising the steps of:

simultaneously accessing an alternate operand for execution of an instruction by using the destination address pointer to address a general register containing the alternate operand; and

selecting at a predetermined time in an instruction execution cycle one of the set of operands including the first operand and the alternate operand.