Advanced parallel array processor (APAP)

• US 5,842,031 A
• Filed: 06/06/1995
• Issued: 11/24/1998
• Est. Priority Date: 11/13/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuchinski, David Christoper, Stupp, James Robert, Retter, Eric Eugene, Schoonover, Nicholas Jerome, Kogge, Peter Michael, Wilkinson, Paul Amba, Dieffenderfer, James Warren, Richardson, Robert Reist, Collins, Clive Allan, Rolfe, David Bruce, Dapp, Michael Charles, Barker, Thomas Norman, Lesmeister, Donald Michael, Miles, Richard Ernest, Smoral, Vincent John, Knowles, Billy Jack, Nier, Richard Edward, Grice, Donald George
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/468,045
• Time in Patent Office: 1,267 Days
• Field of Search: 395/800, 395/800.13, 395/800.2
• US Class Current: 712/23
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Claims

1. A computer system, comprising:

a control unit, an interconnection system and a processing array for parallel processing having nodes which are interconnected with the distribution system to other processing nodes,

means for separating the physical and logical aspects of data transfer, control transfer, and diagnostic and status transfers,

means for the application or system operation software to circumvent the separating, when operating conditions warrant,

means for embedding all data routing and message passing protocols in parallel array software, and wherein

paths and interconnection ports are multi dimensional meshes, with edges wrapped or unwrapped, or topology extensions to multi dimensional tree or hypercube structures, and

each processing element to receives data from four or more other processing elements and transmits data to one processing element all simultaneously

wherein the control unit is programmable and has means for enabling the processing array having an array of processing elements to operate in coordination and which also enables a system control program to operate subsets of the parallel array with each subset dedicated to different applications or different phases of a single application program'"'"'s processing,

the interconnection system provides physical connections between the control unit and the elements of the parallel array of processing elements enabling data and control transfers which are completely independent of the transfer of data between elements of the processing array,

the interconnection system distributes functions associated with data transfer between elements of the processing array and distributed functions embedded in processing node software, and

the processing array provides non-shared memory and compute services and which are partitioned and the processing array is scalable.

2. The computer system of claim 1 further comprising means for processing applications that perform the serial portions of an application task within the controller or within a single element of the processing array, while distributing the parallel portions of the task among processing elements.

3. The computer system of claim 1 wherein the control unit is a microprocessor programmable in a high order language while the parallel operations within the processing array are performed by stored library functions.

4. The computer system of claim 1 wherein the control unit provides the services needed to operate the parallel processing array in either SIMD or MIMD modes, and which also provides switching between the two modes on an instruction-by-instruction basis or on a block-of-instructions by block-of-instructions basis where a block of instructions is any size determined by a control program.

5. The computer system of claim 1 wherein the control unit has means for broadcasting commands and data to the parallel processing array and for reading status, application specified data, and diagnostic data from the parallel processing array,

means for dividing the parallel processing array into partitions,

means for scaling total control capability in proportion to the scaling of the size of the parallel array of processing elements,

means for attaching I/O devices so that the devices are available to the parallel array,

data ports and an internal bus for the parallel array so that the array can be connected to system buses with bandwidths ranging from a few megabytes per second to many gigabytes per second,

means for scaling the number and independence of I/O ports to meet application needs and characteristics, and

an interconnection system providing data paths to the parallel array that are completely independent of and do not interfere with data paths used to communicate information between elements of the parallel array.

6. The computer system of claim 1 wherein applications are processed that perform the serial portions of an application task within the controller or within a single element subarray and its controller of the processing array, while distributing the parallel portions of the task among processing elements.

7. The computer system of claim 1 wherein applications are processed that perform the serial portions of an application task in a SIMIMD mode and wherein a single element can source a broadcast bus of the processing array, while distributing the parallel portions of the task among processing elements.

8. The computer system of claim 1 wherein the control unit including a controller which has

means for broadcasting commands and data to the parallel processing array and for reading status, application specified data, and diagnostic data from the parallel processing array, and means for dividing the parallel processing array into partitions,

means for attaching total control capability in proportion to the scaling of the size of the parallel array of processing elements,

means for attaching I/O devices so that the devices are available to the parallel array,

data ports and an internal bus for the parallel array so that the array connected to system buses with bandwidths ranging from a few megabytes per second to many gigabytes per second,

means for scaling the number and independence of I/O ports to meet the application needs and characteristics, and

an interconnection system providing data paths to the parallel array that are completely independent of and do not interfere with data paths used to communicate information between elements of the parallel array.