Diode-based semiconductor read-only memory device and method of fabricating the same

• US 5,843,824 A
• Filed: 04/15/1997
• Issued: 12/01/1998
• Est. Priority Date: 02/17/1997
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, Jih-Wen, Wen, Jemmy
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/838,152
• Time in Patent Office: 595 Days
• Field of Search: 438/130, 438/237, 438/275, 438/276, 438/278, 438/296
• US Class Current: 438/278
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A diode-based ROM device and a method for fabricating the same are provided. The ROM device is of the type including an array of diode-based memory cells for permanent storage of binary-coded data therein. In the semiconductor structure of the ROM device, a plurality of insulator-filled trenches are formed for isolation of the diode-based memory cells. This feature allows the prevention of the punch-through effect when the ROM device is downsized. Further, the bit lines for the ROM device are formed with an increased junction depth such that the resistance of the bit lines can be reduced to allow an increase in the magnitude of the currents in the bit lines for easier detection and distinguishing of the binary state the currents represent. In accordance with the method, the mask-programming process can be easily implemented by forming contact windows at predetermined locations that are associated with the memory cells that are to be set to a permanently-ON state, and then doping an impurity material through the contact windows into an upper portion of the associated bit lines to form a junction diode thereon. The memory cells that are not formed with diodes are set to a permanently-OFF state.

Claims

1. A method for fabricating a diode-based ROM device, comprising the steps of:

(1) preparing a semiconductor substrate of a first semiconductor type, and then forming a plurality of substantially parallel-spaced trenches on a surface of the substrate in a first direction;

(2) forming a first insulating layer over the substrate, the first insulating layer filling up all of the trenches on the substrate;

(3) removing a thickness of the first insulating layer other than the portions in the trenches;

(4) performing a first ion-implantation process so as to dope a first impurity material of a second semiconductor type into those portions of the substrate that are located between the trenches to form a plurality of substantially parallel-spaced first diffusion regions of the second semiconductor type between the trenches, the first diffusion regions serving as a plurality of bit lines for the ROM device on which a plurality of memory cells are defined;

(5) forming a second insulating layer which covers all of the first diffusion regions and all of the remaining portions of the first insulating layer in the trenches;

(6) forming a plurality of contact windows in the second insulating layer so as to expose a selected group of the first diffusion regions that are associated with a first selected group of the memory cells of the ROM device that are to be set to a permanently-ON state;

(7) by using the second insulating layer as a mask, performing a second ion-implantation process so as to dope a second impurity material of the first semiconductor type into an upper portion of each of the exposed first diffusion regions so as to form a plurality of second diffusion regions of the first semiconductor type respectively in the upper portion of each of the exposed first diffusion regions;

each of the second diffusion regions and the associated one of the first diffusion regions in combination constituting a junction diode;

(8) forming a conductive layer over the second insulating layer, which fills up all of the contact windows in the second insulating layer to come in electrical contact with all of the second diffusion regions; and

(9) removing selected portions of the conductive layer so as to form a plurality of substantially parallel-spaced word lines in a second direction.

2. The method of claim 1, wherein the first semiconductor type is P-type while the second semiconductor type is N-type.

3. The method of claim 1, wherein the first semiconductor type is N-type while the second semiconductor type is P-type.

4. The method of claim 1, wherein in said step (2), the first insulating layer is a layer of silicon dioxide.

5. The method of claim 1, wherein in said step (3), the thickness of the first insulating layer is removed by performing a CMP process.

6. The method of claim 1, wherein in said step (3), the thickness of the first insulating layer is removed by performing an anisotropic etching-back process.

7. The method of claim 1, wherein in said step (4), the first diffusion regions are each formed by doping to a depth less than the depth of the trenches in the substrate.

8. The method of claim 1, wherein in said step (5), the second insulating layer is a layer of silicon dioxide.

9. The method of claim 1, wherein in said step (5), the second insulating layer is a layer of silicon nitride.

10. The method of claim 1, wherein in said step (8), the conductive layer is a layer of highly-doped polysilicon.

11. The method of claim 1, wherein in said step (8), the conductive layer is a metallization layer.

12. The method of claim 1, wherein in said step (9), the second direction is oriented substantially at a right angle with respect to the first direction.