Consolidated chip design for wire bond and flip-chip package technologies

• US 5,844,317 A
• Filed: 07/26/1996
• Issued: 12/01/1998
• Est. Priority Date: 12/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gramatski, Eberhard, Fiore, James, Bertolet, Allan
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/686,855
• Time in Patent Office: 858 Days
• Field of Search: 257/780, 257/781, 257/784, 257/787, 257/774, 257/773
• US Class Current: 257/773
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier

Abstract

A semiconductor structure and method of fabrication are provided in which permanent external electrical connection to active circuitry in the structure can be made through either a wire bond pad or metal bump formed thereon. A final metallization including a wire bond pad is disposed over and electrically connected with the active circuitry. An insulating material film is disposed over the final metallization leaving the wire bond pad and a portion of the final metallization laterally displaced from the pad exposed. A metal bump contacts the laterally displaced exposed portion of the final metallization. The wire bond pad is electrically coupled with and laterally displaced from the metal bump through the final metallization. The metal bump and wire bond pad are configured to facilitate electrical connection of the semiconductor structure with an external connector, such as a modular packaging substrate. The structure may also be used for testing and burning in a semiconductor die without direct physical contact of the external testing device to the wire bond pad.

Claims

1. A semiconductor structure facilitating external electrical connection to a region of active circuitry thereof, through a wire bond pad or a metal bump formed therein, said semiconductor structure comprising:

a semiconductor substrate having said region of active circuitry associated therewith;

a final metallization overlying said semiconductor substrate and electrically connected with said region of active circuitry, said final metallization having an exposed, planar wire bond pad configured to facilitate electrical connection with an external connector;

an insulating material film disposed over said final metallization, said wire bond pad thereof being exposed through a contact hole in said insulating material film, said insulating material film also having a via hole laterally displaced from said contact hole, said via hole exposing a portion of said final metallization laterally displaced from said wire bond pad; and

a metal bump disposed in said via hole contacting said final metallization, said metal bump being configured to facilitate electrical connection of an external connector thereto, said metal bump being laterally displaced from said wire bond pad and electrically coupled thereto through said final metallization, such that electrical connection to said region of active circuitry of said semiconductor substrate can occur through either said metal bump or said wire bond pad.

2. The structure according to claim 1, wherein said metal bump is also partially disposed on said insulating material film adjacent said via hole such that said metal bump is physically adhered to said insulating material film.

3. The structure according to claim 2 further comprising an adhesive conductive film interposed between said metal bump and said insulating material film and between said metal bump and said exposed portion of said final metallization laterally displaced from said wire bond pad, said adhesive conductive film facilitating adherence of said metal bump to said insulating material film and to said exposed final metallization.

4. The structure according to claim 3, wherein said adhesive conductive film comprises a first layer of chromium or titanium.

5. The structure according to claim 4, wherein said adhesive conductive film further comprises a layer of copper on said first layer and a layer of gold on said copper layer.

6. The structure according to claim 1, wherein said metal bump is selected from a group consisting of a solder ball, an aluminum bump, and a gold bump.

7. The structure according to claim 1, wherein said insulating material film comprises an insulator selected from a group consisting of silicon dioxide, silicon nitride, and polyimide.

8. The structure according to claim 1, wherein said insulating material film comprises a dielectric layer and a final passivation layer disposed on said dielectric layer.

9. The structure according to claim 8, wherein said dielectric layer comprises an insulator selected from a group consisting of silicon dioxide, silicon nitride, and polyimide.

10. The structure according to claim 8, wherein said final passivation layer comprises an insulator selected from a group consisting of silicon dioxide, silicon nitride, and polyimide.

17. The structure according to claim 1, wherein said metal bump comprises a controlled collapse chip connect (C4) type solder ball which partially resides within said via hole in said insulating material film disposed over said final metallization.

11. A semiconductor die configured to facilitate electrical connection of an external connector thereto through a plurality of metal bumps and a plurality of wire bond pads, said semiconductor die comprising:

a semiconductor substrate having a region of active circuitry associated therewith and an overlying metallization level, said metallization level being electrically coupled to said region of active circuitry;

an inter-level dielectric layer disposed over said metallization level, said inter-level dielectric layer having a plurality of grooves formed in an upper surface thereof, at least two of said plurality of grooves having an aperture formed therein exposing a portion of said metallization level, each groove being spaced from all other grooves of said plurality of grooves;

a conductive metal filling each of said plurality of grooves and each of said corresponding apertures to form a plurality of final metallization lines and a plurality of integral corresponding studs, respectively, each of said plurality of final metallization lines having a wire bond pad, thereby defining a plurality of wire bond pads electrically coupled to said region of active circuitry through said plurality of final metallization lines and said plurality of corresponding studs, each wire bond pad of said plurality of wire bond pads being configured to facilitate electrical connection of an external connector thereto;

an insulating material film disposed over said plurality of final metallization lines, said plurality of wire bond pads being exposed through a plurality of corresponding contact holes in said insulating material film, said insulating material film also having a plurality of via holes therein, each via hole being laterally displaced from a corresponding contact hole and exposing a portion of each underlying final metallization line laterally displaced from a corresponding exposed wire bond pad; and

a plurality of metal bumps, each metal bump being disposed in a corresponding via hole, contacting a corresponding final metallization line, and being electrically interconnected thereby to a corresponding wire bond pad of said plurality of wire bond pads, each metal bump being laterally displaced from said corresponding wire bond pad and being configured to facilitate electrical connection of an external connector thereto, such that electrical connection to said region of active circuitry of said semiconductor substrate can occur through either said plurality of metal bumps or said plurality of wire bond pads.

12. The semiconductor die according to claim 11, wherein each metal bump is also partially disposed on said insulating material film adjacent said corresponding via hole such that each metal bump is physically adhered to said insulating material film.

13. The semiconductor die according to claim 12 further comprising an adhesive conductive film interposed between each metal bump and said insulatingmaterial film and between each metal bump and each corresponding exposed portion of said corresponding final metallization line laterally displaced from said corresponding wire bond pad, said adhesive conductive film facilitating adherence of each metal bump to said insulating material film and to said corresponding exposed final metallization line.

14. The semiconductor die according to claim 11, wherein each metal bump comprises a solder ball, an aluminum bump, or a gold bump.

15. A structure facilitating testing and burn-in of a semiconductor die having a region of active circuitry associated therewith, said semiconductor die also including a final metallization overlying and electrically connected with said region of active circuitry, said final metallization having an exposed, planar wire bond pad therein, said structure comprising:

an insulating material film disposed over said final metallization, said wire bond pad thereof being exposed through a contact hole in said insulating material film, said insulating material film also having a via hole laterally displaced from said contact hole, said via hole exposing a portion of said final metallization laterally displaced from said wire bond pad; and

an auxiliary testing terminal disposed in said via hole contacting said final metallization, said auxiliary testing terminal being laterally displaced from said wire bond pad and electrically coupled thereto through said final metallization, said auxiliary testing terminal being configured to facilitate connection of an external test device thereto such that electrical testing of said semiconductor die can occur through said auxiliary testing terminal without direct physical contact of said external test device to said wire bond pad.

16. The structure according to claim 15, wherein said auxiliary testing terminal comprises a metal bump.