Differential flipflop circuit operating with a low voltage

• US 5,844,437 A
• Filed: 03/28/1997
• Issued: 12/01/1998
• Est. Priority Date: 03/28/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yoshida, Jun, Asazawa, Hiroshi, Uemura, Gohiko
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US08/825,390
• Time in Patent Office: 613 Days
• Field of Search: 327/199-204, 327/208, 327/210-212, 327/214-219
• US Class Current: 327/202
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/289 of the master-slave type

Abstract

In a flipflop circuit, each of master and slave latch/hold circuits is constituted of differential pairs consisting of transistors each connected between VCC and VSS without being in series with another transistor between VCC and VSS. A clock driving circuit has a pull-down function responding to a pair of complementary clocks so as to pull down the level of a pair of complementary data signals supplied to each latch/hold circuit. With this arrangement, the flipflop circuit composed of bipolar transistors can operate with a low voltage of not greater than 1 V.

Claims

1. A flipflop circuit comprising:

a master latch/hold circuit latching and holding a pair of complementary input data signals in synchronism with a pair of complementary clocks for outputting a pair of complementary master data signals, said master latch/hold circuit including;

first and second transistors having their emitters connected together and the base of the first transistor connected to receive one of said pair of complementary input data signals and the base of the second transistor connected to receive the other of said pair of complementary input data signals,

third and fourth transistors having their emitters connected together and connected in common with said emitters of said first and second transistors, the collector of said third transistor being connected to the collector of said first transistor and the collector of said fourth transistor being connected to the collector of said second transistor, and the collector of said third transistor being directly connected to the base of said fourth transistor and the collector of said fourth transistor being directly connected to the base of said third transistor,

a first constant current source connected between the common-connected emitters of said first, second, third and fourth transistors and a first power supply voltage,

first and second resistors, each having one of its two ends connected in common to a second power supply voltage, the other end of the first resistor being connected to the common-connected collectors of said first and third transistors, and the other end of the second resistor being connected to the common-connected collectors of said second and fourth transistors,

wherein the common-connected collectors of said first and third transistors and the common-connected collectors of said second and fourth transistors output said pair of complementary master data signals;

a slave latch/hold circuit latching and holding a pair of complementary slave input data signals corresponding to said pair of complementary master data signals, in synchronism with said pair of complementary clocks, for outputting a pair of complementary output data signals, said slave latch/hold circuit including;

fifth and sixth transistors having their emitters connected together and the base of said fifth transistor being connected to receive on of said pair of complementary slave input data signals and the base of the sixth transistor being connected to receive the other of said pair of complementary slave input data signals,

seventh and eighth transistors having their emitters connected together and in common with the common-connected emitters of said fifth and sixth transistors, the collector of said seventh transistor being connected to the collector of said fifth transistor, the collector of said eighth transistor being connected to the collector of said sixth transistor, the collector of said seventh transistor being directly connected to the base of said eighth transistor, and the collector of said eighth transistor being directly connected to the base of said seventh transistor,

a second constant current source connected between the common-connected emitters of said fifth, sixth, seventh and eighth transistors and said first power supply voltage,

third and fourth resistors, each having one of its two ends connected in common to said second power supply voltage, the other end of the third resistor being connected to the common-connected collectors of said fifth and seventh transistors, and the other end of the fourth resistor being connected to the common-connected collectors of said sixth and eighth transistors,

wherein the common-connected collectors of said fifth and seventh transistors and the common-connected collectors of said sixth and eighth transistors output said pair of complementary output data signals; and

a clock driving circuit receiving at least one of said pair of complementary clocks for driving said master latch/hold and slave latch/hold circuits to cause said master latch/hold and slave latch/hold circuits to operate in synchronism with each other, said clock driving circuit having a pull-down circuit for lowering respective potential levels of said pair of complementary input data signals and said pair of complementary master data signals, in response to said pair of complementary clocks.

2. A flipflop circuit according to claim 1 wherein said master latch/hold circuit further includes a fifth resistor connected between said second power supply voltage and the common-connected one ends of said first and second resistor, and said slave latch/hold circuit further includes a sixth resistor connected between said second power supply voltage and the common-connected one ends of said third and fourth resistors.

3. A flipflop circuit according to claim 1 wherein said clock driving circuit includes;

ninth and tenth transistors having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said first and sixth transistors, respectively;

eleventh and twelfth transistors having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said second and fifth transistors, respectively;

a third constant current source connected between the common-connected emitters of said ninth and tenth transistors and said first power supply voltage; and

a fourth constant current source connected between the common-connected emitters of said eleventh and twelfth transistors and said first power supply voltage.

4. A flipflop circuit according to claim 1 further including:

a first data buffer receiving and amplifying a pair of complementary supplied data signals for outputting said pair of complementary input data signals to said master latch/hold circuit; and

a second data buffer receiving and amplifying said pair of complementary master data signals for outputting said pair of complementary slave input data signals to said slave latch/hold circuit.

5. A flipflop circuit according to claim 4,

wherein said first data buffer includes thirteenth and fourteenth transistors having their emitters connected in common and their bases connected to receive said pair of complementary supplied data signals, respectively, and their collectors for outputting said pair of complementary input data signals, respectively, seventh and eighth resistors connected between said collectors of said thirteenth and fourteenth transistors and said second power supply voltage, respectively, and a fifth constant current source connected between the common-connected emitters of said thirteenth and fourteenth transistors and said first power supply voltage, and

wherein said second data buffer includes:

fifteenth and sixteenth transistors having their emitters connected in common and their bases connected to receive said pair of complementary master data signals, respectively, and their collectors for outputting said pair of complementary slave input data signals, respectively, ninth and tenth resistors connected between the collectors of said fifteenth and sixteenth transistors and said second power supply voltage, respectively, and a sixth constant current source connected between the common-connected emitters of said fifteenth and sixteenth transistors and said first power supply voltage.

6. A flipflop circuit comprising:

a master latch/hold circuit latching and holding a pair of complementary input data signals in synchronism with a pair of complementary clocks for outputting a pair of complementary master data signals, said master latch/hold circuit including;

first and second transistors having their emitters connected in common, and the base of said first transistor being connected to receive one of said pair of complementary input data signals, and the base of said second transistor being connected to receive the other of said pair of complementary input data signals,

third and fourth transistors having their emitters connected together in common with said emitters of said first and second transistors, the collector of said third transistor being connected to the collector of said first transistor, and the collector of said fourth transistor being connected to the collector of said second transistor, and the collector of said third transistor being connected to the base of said fourth transistor, and the collector of said fourth transistor being connected to the base of said third transistor,

a first constant current source connected between the common-connected emitters of said first, second, third and fourth transistors and a first power supply voltage, and

first and second resistors, each having one of its two ends connected in common to a second power supply voltage, the other end of said first resistor being connected to the common-connected collectors of said first and third transistors, and the other end of said second resistor being connected to the common-connected collectors of said second and fourth transistors,

wherein the common-connected collectors of said first and third transistors and the common-connected collectors of said second and fourth transistors output said pair of complementary master data signals;

a slave latch/hold circuit latching and holding a pair of complementary slave input data signals corresponding to said pair of complementary master data signals, in synchronism to said pair of complementary clocks, for outputting a pair of complementary output data signals, said slave latch/hold circuit including;

fifth and sixth transistors having their emitters connected in common, the base of said fifth transistor being connected to receive one of said pair of complementary slave input data signals, and the base of said sixth transistor being connected to receive the other of said pair of complementary slave input data signals,

seventh and eighth transistors having their emitters connected together and in common with the common-connected emitters of said fifth and sixth transistors, the collector of said seventh transistor being connected to the collector of said fifth transistor, and the collector of the eighth transistor being connected to the collector of the sixth transistor, the collector of said seventh transistor being connected to the base of said eighth transistor, and the collector of said eighth transistor being connected to the base of said seventh transistor,

a second constant current source connected between the common-connected emitters of said fifth, sixth, seventh and eighth transistors and said first power supply voltage,

third and fourth resistors, each having one of its two ends connected in common to said second power supply voltage, and the other end of the third resistor being connected to the common-connected collectors of said fifth and seventh transistors, and the other end of said fourth resistor being connected to the common-connected collectors of said sixth and eighth transistors,

wherein the common-connected collectors of said fifth and seventh transistors and the common-connected collectors of said sixth and eighth transistors output said pair of complementary output data signals;

a clock driving circuit receiving said pair of complementary clocks for driving said master latch/hold and slave latch/hold circuits to cause said master latch/hold and slave latch/hold circuits to operate in synchronism with each other, said clock driving circuit including;

ninth and tenth transistors having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said first and sixth transistors, respectively,

eleventh and twelfth transistors, having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said second and fifth transistors, respectively,

a third constant current source connected between the common-connected emitters of said ninth and tenth transistors and said first power supply voltage, and

a fourth constant current source connected between the common-connected emitters of said eleventh and twelfth transistors and said first power supply voltage;

a first data buffer receiving and amplifying a pair of externally supplied complementary data signals for outputting said pair of complementary input data signals to said master latch/hold circuit, said data buffer including;

thirteenth and fourteenth transistors having their emitters connected in common and their bases connected to receive said pair of externally supplied complementary data signals, respectively,

seventh and eighth resistors, each having one of its two ends connected to said second power supply voltage, the other end of said seventh resistor being connected to the collector of said thirteenth transistor, and the other end of said eighth resistor being connected to the collector of said fourteenth transistor,

a fifth constant current source connected between the common-connected emitters of said thirteenth and fourteenth transistors and said first power supply voltage,

the collector of said thirteenth transistor being connected to the base of said second transistor and the collector of said eleventh transistor, and the collector of said fourteenth transistor being connected to the base of said first transistor and the collector of said ninth transistor, so that the collectors of said thirteenth and fourteenth transistors output said pair of complementary input data signals; and

a second data buffer receiving and amplifying said pair of complementary master data signals for outputting said pair of complementary slave input data signals to said slave latch/hold circuit, said second data buffer including;

fifteenth and sixteenth transistors having their emitters connected in common, the base of said fifteenth transistor being connected to the collector of said second and fourth transistors, and the base of said sixteenth transistor being connected to the collector of said first and third transistors,

ninth and tenth resistors, each having one of its two ends connected to said second power supply voltage, the other end of said ninth resistor being connected to the collector of said fifteenth transistor and the other end of the tenth resistor being connected to the collector of the sixteenth transistor,

a sixth constant current source connected between the common-connected emitters of said fifteenth and sixteenth transistors and said first power supply voltage,

the collector of said fifteenth transistor being connected to the base of said sixth transistor and the collector of said tenth transistor, and the collector of said sixteenth transistor being connected to the base of said fifth transistor and the collector of said twelfth transistor, so that the collectors of said fifteenth and sixteenth transistors output said pair of complementary slave input data signals.

7. A flipflop circuit according to claim 6,

wherein said master latch/hold circuit further includes a fifth resistor connected between said second power supply voltage and the common-connected one ends of said first and second resistors, and

wherein said slave latch/hold circuit further includes a sixth resistor connected between said second power supply voltage and the common-connected one ends of said third and fourth resistors.

8. A flipflop circuit comprising:

a master latch/hold circuit latching and holding a pair of complementary input data signals in synchronism with a pair of complementary clocks for outputting a pair of complementary master data signals, said master latch/hold circuit including;

first and second transistors having their emitters connected in common, and the base of said first transistor being connected to receive one of said pair of complementary input data signals, and the base of said second transistor being connected to receive the other of said pair of complementary input data signals,

third and fourth transistors having their emitters connected together in common with said emitters of said first and second transistors, the collector of said third transistor being connected to the collector of said first transistor, and the collector of said fourth transistor being connected to the collector of said second transistor, and the collector of said third transistor being connected to the base of said fourth transistor, and the collector of said fourth transistor being connected to the base of said third transistor,

a first constant current source connected between the common-connected emitters of said first, second, third and fourth transistors and a first power supply voltage, and

first and second resistors, each having one of its two ends connected in common to a second power supply voltage, the other end of said first resistor being connected to the common-connected collectors of said first and third transistors, and the other end of said second resistor being connected to the common-connected collectors of said second and fourth transistors,

wherein the common-connected collectors of said first and third transistors and the common-connected collectors of said second and fourth transistors output said pair of complementary master data signals;

a slave latch/hold circuit latching and holding a pair of complementary slave input data signals corresponding to said pair of complementary master data signals, in synchronism to said pair of complementary clocks, for outputting a pair of complementary output data signals, said slave latch/hold circuit including;

fifth and sixth transistors having their emitters connected in common, the base of said fifth transistor being connected to receive one of said pair of complementary slave input data signals, and the base of said sixth transistor being connected to receive the other of said pair of complementary slave input data signals,

seventh and eighth transistors having their emitters connected together and in common with the common-connected emitters of said fifth and sixth transistors, the collector of said seventh transistor being connected to the collector of said fifth transistor, and the collector of the eighth transistor being connected to the collector of the sixth transistor, the collector of said seventh transistor being connected to the base of said eighth transistor, and the collector of said eighth transistor being connected to the base of said seventh transistor,

a second constant current source connected between the common-connected emitters of said fifth, sixth, seventh and eighth transistors and said first power supply voltage,

third and fourth resistors, each having one of its two ends connected in common to said second power supply voltage, and the other end of the third resistor being connected to the common-connected collectors of said fifth and seventh transistors, and the other end of said fourth resistor being connected to the common-connected collectors of said sixth and eighth transistors,

wherein the common-connected collectors of said fifth and seventh transistors and the common-connected collectors of said sixth and eighth transistors output said pair of complementary output data signals;

a clock driving circuit receiving said pair of complementary clocks for driving said master latch/hold and slave latch/hold circuits to cause said master latch/hold and slave latch/hold circuits to operate in synchronism with each other, said clock driving circuit including;

ninth and tenth transistors having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said first and sixth transistors, respectively,

eleventh and twelfth transistors, having their emitters connected in common and their bases connected to receive said pair of complementary clocks, respectively, and their collectors connected to said bases of said second and fifth transistors, respectively,

a third constant current source connected between the common-connected emitters of said ninth and tenth transistors and said first power supply voltage, and

a fourth constant current source connected between the common-connected emitters of said eleventh and twelfth transistors and said first power supply voltage.

9. A flipflop circuit according to claim 8 further including:

a first data buffer receiving and amplifying a pair of externally supplied complementary data signals for outputting said pair of complementary input data signals to said master latch/hold circuit, said data buffer including;

thirteenth and fourteenth transistors having their emitters connected in common and their bases connected to receive said pair of externally supplied complementary data signals, respectively,

seventh and eighth resistors, each having one of its two ends connected to said second power supply voltage, the other end of said seventh resistor being connected to the collector of said thirteenth transistor, and the other end of said eighth resistor being connected to the collector of said fourteenth transistor,

a fifth constant current source connected between the common-connected emitters of said thirteenth and fourteenth transistors and said first power supply voltage,

the collector of said thirteenth transistor being connected to the base of said second transistor and the collector of said eleventh transistor, and the collector of said fourteenth transistor being connected to the base of said first transistor and the collector of said ninth transistor, so that the collectors of said thirteenth and fourteenth transistors output said pair of complementary input data signals; and

a second data buffer receiving and amplifying said pair of complementary master data signals for outputting said pair of complementary slave input data signals to said slave latch/hold circuit, said second data buffer including;

fifteenth and sixteenth transistors having their emitters connected in common, the base of said fifteenth transistor being connected to the collector of said second and fourth transistors, and the base of said sixteenth transistor being connected to the collector of said first and third transistors,

ninth and tenth resistors, each having one of its two ends connected to said second power supply voltage, the other end of said ninth resistor being connected to the collector of said fifteenth transistor and the other end of the tenth resistor being connected to the collector of the sixteenth transistor,

a sixth constant current source connected between the common-connected emitters of said fifteenth and sixteenth transistors and said first power supply voltage,

the collector of said fifteenth transistor being connected to the base of said sixth transistor and the collector of said tenth transistor, and the collector of said sixteenth transistor being connected to the base of said fifth transistor and the collector of said twelfth transistor, so that the collectors of said fifteenth and sixteenth transistors output said pair of complementary slave input data signals.

10. A flipflop circuit according to claim 9,

wherein said master latch/hold circuit further includes a fifth resistor connected between said second power supply voltage and the common-connected one ends of said first and second resistors, and

wherein said slave latch/hold circuit further includes a sixth resistor connected between said second power supply voltage and the common-connected one ends of said third and fourth resistors.