DC restoration circuit for multi-level transmission signals

• US 5,844,439 A
• Filed: 03/13/1996
• Issued: 12/01/1998
• Est. Priority Date: 03/13/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Integrated Circuit Systems, Incorporated (Renesas Electronics Corporation)
• Inventors: Zortea, Anthony E.
• Primary Examiner(s): Chan, Jason
• Assistant Examiner(s): Corrielus, Jean B
• Application Number:
  US08/596,885
• Time in Patent Office: 993 Days
• Field of Search: 375/317, 375/319, 375/377, 375/219, 375/287, 375/257, 327/362, 327/363, 327/307, 327/45, 327/44, 327/39, 327/312, 327/323, 327/321, 327/332, 455/14, 455/67.1, 455/226.1, 455/234.1, 455/234.2
• US Class Current: 327/307
• CPC Class Codes: H03K 5/007 Base line stabilisation thresholding H03K5/08

Abstract

A DC restoration circuit to correct for baseline wandering in a data receiver is provided. A voltage correction circuit is connected to the received data line to adjust the voltage level of the received data dynamically. The voltage correction circuit is controlled by a feedback circuit which includes a voltage detection circuit configured to detect the peak voltage levels or envelope of the received data. This detected level is then compared to a reference level, and the result of the comparison is used as a control signal for the voltage correction circuit.

Claims

1. A DC restoration circuit for a data receiver, comprising:

a received data line configured to receive a multi-level transmission;

a voltage correction circuit coupled to said received data line and configured to adjust a voltage level of said multi-level transmission;

a feedback circuit having an input connected to said data line and an output coupled to a control input of said voltage correction circuit, said feedback circuit including

a detection circuit configured to detect a baseline wander of received data, and

a comparison circuit configured to generate a control signal to said control input of said voltage correction circuit in response to a comparison of an output of said detection circuit to a voltage reference;

a first resistor coupled in series in said received data line; and

a second resistor coupled to an output node of said first resistor,

said voltage correction circuit including

a diode coupled between an output of said comparison circuit and said second resistor, and

a capacitor coupled between said output of said comparison circuit and ground.

2. A DC restoration circuit for a data receiver, comprising:

a first resistance coupling a received data line to a correction node;

a baseline wander detector having an input coupled to said correction node;

a comparison circuit having a first input coupled to an output of said baseline wander detector, a second input coupled to a reference voltage, and an output;

a capacitor coupled to said output of said comparison circuit; and

a second resistor coupled between said output of said comparison circuit and said correction node.

3. The DC restoration circuit of claim 2 wherein said baseline wander detector is configured to have a response time greater than a DC wander range and less than a slowest data rate.

4. The DC restoration circuit of claim 2 wherein said comparison circuit comprises an operational transconductance amplifier.

5. The DC restoration circuit of claim 4 further comprising a buffer connected between said second resistor and said capacitor.

6. A data transceiver comprising:

a data receiver input;

an equalizer coupled to said data receiver input;

a first resistor having a first node coupled to an output of said equalizer;

a slicer circuit coupled to a second node of said first resistor;

a voltage correction circuit connected to said second node and configured to adjust a voltage level of the received data;

a feedback circuit having an input coupled to said second node and an output coupled to a control input of said voltage correction circuit, said feedback circuit including

a detection circuit configured to detect a low frequency voltage level of received data, and

a comparison circuit configured to generate a control signal to said control input of said voltage correction circuit in response to a comparison of an output of said detection circuit to a voltage reference.

7. The transceiver of claim 6 wherein said feedback circuit is configured to have a response time greater than a DC wander range and less than a slowest data rate.

8. The transceiver of claim 6 wherein said detection circuit comprises a peak detector for detecting an envelop of said received data.

9. The transceiver of claim 6 wherein said comparison circuit comprises an operational transconductance amplifier.

10. The transceiver of claim 6 further comprising a second resistor coupled to an output node of said first resistor, and wherein said voltage correction circuit comprises:

a buffer coupled between an output of said comparison circuit and said second resistor, and

a capacitor coupled between said output of said comparison circuit and ground.