Television with integrated receiver decoder

• US 5,844,623 A
• Filed: 09/27/1996
• Issued: 12/01/1998
• Est. Priority Date: 09/27/1996
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Iwamura, Ryuichi
• Primary Examiner(s): Hsia, Sherrie
• Application Number:
  US08/722,631
• Time in Patent Office: 795 Days
• Field of Search: 348/553, 348/555, 348/556, 348/557, 348/725, 348/728, 348/558, 348/563
• US Class Current: 725/70
• CPC Class Codes: H04N 5/445 for displaying additional information H04N5/50 takes precedence
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

A television set includes an integrated receiver decoder. By integrating the receiver/decoder with the television, some circuitry and memory are shared. Moreover, a digital video signal provided by the receiver/decoder need not be converted to an analog NTSC signal before transmission to the television CRT. In one embodiment, where a television having a 16×9 aspect ratio is used, on-screen display data is displayed without distortion.

Claims

1. A television, comprising:

first circuitry configured to decode and display television signals having a first signal format; and

second circuitry coupled to said first circuitry configured to decode and display television signals having a second signal format and further configured to encode said television signals in said first signal format.

2. A television as in claim 1 wherein said first signal format is an NTSC format and said second signal format is an MPEG format.

3. A television as in claim 2 wherein said first circuitry comprises:

a first processor for separating luminance and chrominance information present in said NTSC format; and

a second processor coupled to said first processor for generating RGB signals from said luminance and chrominance information.

4. A television as in claim 3 wherein said first processor includes a memory shared by said second circuitry.

5. A television as in claim 4 wherein said second circuitry comprises:

a video decoder coupled to said memory, said video decoder for decoding MPEG video signals present within said television signals having said MPEG format; and

an audio decoder coupled to said memory, said audio decoder for decoding MPEG audio signals present within said television signals having said MPEG format.

6. A television as in claim 5 wherein said television signals having said MPEG format are encrypted prior to being transmitted and said second circuitry further comprises decryption means coupled to said memory for decrypting said encrypted television signals.

7. A television as in claim 5 wherein said second circuitry comprises a digital satellite system integrated receiver decoder.

8. A method of mixing on-screen display data with video data for presentation on a television, the method comprising the steps of:

decoding said video data from a received television signal to produce decoded video data;

decoding said on-screen display data from said received television signal to produce decoded on-screen display data;

expanding said decoded video data to produce expanded aspect ratio format video data; and

mixing said expanded aspect ratio format video data with said decoded on-screen display data to produce a mixed signal.

9. The method of claim 8 further comprising the step of encoding said mixed signal in a format for presentation on the television.

10. The method of claim 9 wherein said format is an NTSC format.