Cell array structure for a ferroelectric semiconductor memory and a method for sensing data from the same

• US 5,844,832 A
• Filed: 08/22/1997
• Issued: 12/01/1998
• Est. Priority Date: 08/22/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yun-Gi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/916,207
• Time in Patent Office: 466 Days
• Field of Search: 365/145, 365/189.01, 365/230.01, 365/210
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A ferroelectric semiconductor random access memory (RAM) is disclosed, which comprises a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells having an access transistor and a ferroelectric capacitor, a plurality of bit lines of open bit line structure connected with corresponding sense amplifiers, and a plurality of reference cells arranged symmetrically against the sense amplifiers for providing reference voltage to the reference input terminals of the sense amplifiers toe sense the logical states of the data stored in the memory cells. In this device, the reference voltage is provided from one of the reference cells.

Claims

1. A ferroelectric semiconductor random access memory, comprising

a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells comprising an access transistor and a ferroelectric transistor;

a plurality of bit lines connected with corresponding sense amplifiers; and

a plurality of reference cells arranged symmetrically against the sense amplifiers for providing reference voltage to the reference input terminals of the sense amplifiers to sense the logical states of data stored in the memory cells,

wherein the reference voltage is provided from one of the reference cells.

2. A ferroelectric semiconductor memory as recited in claim 1, wherein the bitlines are of an open bit line structure.

3. A ferroelectric semiconductor memory, comprising:

a plurality of sense amplifiers connected to corresponding bit lines;

a plurality of ferroelectric memory cells arranged symmetrically against the sense amplifiers and connected between the bit lines and plate lines; and

a pair of reference cells arranged symmetrically against each of the sense amplifiers and connected with the bit lines so as to be outside the memory cells,

wherein each of the reference cells comprises a capacitor with a capacitance equal to half the polarization capacitance of the ferroelectric capacitor of the memory cell, and

wherein the reference voltage for the sense amplifier to sense the data of a selected memory cell in a data read mode is supplied at the half level of a binary data from the reference cell opposite to the selected memory cell with respect to the sense amplifier.

4. A ferroelectric semiconductor memory as recited in claim 3, wherein the bitlines are of an open bit line structure.

5. A ferroelectric semiconductor memory as recited in claim 3, wherein the capacitors in the reference cells are ferroelectric capacitors.

6. A ferroelectric semiconductor memory as recited in claim 5, wherein the contact size between the ferroelectric layer of the reference cell and an upper electrode of the reference cell is smaller than a contact size between that of the memory cell and the upper electrode.

7. A ferroelectric semiconductor memory as recited in claim 5, wherein the contact size between the ferroelectric layer of the reference cell and an upper electrode of the reference cell is greater than the contact size between that of the memory cell and the upper electrode.

8. A ferroelectric semiconductor memory as recited in claim 3, wherein the reference cells comprise MOS capacitors.

9. A method for sensing data from memory cells in a ferroelectric semiconductor random access memory including a memory cell array having a plurality of the memory cells arranged in a matrix, each of the memory cells having an access transistor, a ferroelectric capacitor, a plurality of bit lines of open bit line structure connected with corresponding sense amplifiers, and a plurality of reference cells arranged symmetrically against the sense amplifiers for providing reference voltage to the reference input terminals of the sense transistor to sense the logical states of the data stored in said memory cells, the method comprising the steps of:

supplying a voltage representing a logical state of data stored in a selected memory cell to a sensing input of a sense amplifier;

supplying a reference voltage to the sense amplifier; and

comparing the voltage of the sensing input with the reference voltage to amplify the voltage difference between them,

wherein the reference voltage for the sense amplifier is at half the level of a bit of binary data stored in a reference cell opposite to the selected memory cell with respect to the sense amplifier.