High voltage NMOS pass gate having supply range, area, and speed advantages

• US 5,844,840 A
• Filed: 08/19/1997
• Issued: 12/01/1998
• Est. Priority Date: 08/19/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chen, Pau-Ling, Hollmer, Shane Charles, Hu, Chung-You, Derhacobian, Narbeh, Le, Binh Quang
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US08/914,543
• Time in Patent Office: 469 Days
• Field of Search: 365/185.23, 365/230.06, 365/226
• US Class Current: 365/185.23
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.

Claims

1. A high voltage pass gate, comprising:

first and second coupling capacitors each having upper and lower plates;

a plurality of transistors, each transistor having a corresponding gate, source, and drain, wherein the plurality of transistors comprises;

first, second, and third series boost transistors;

first and second isolation boost transistors;

wherein the first series boost transistor source, the second isolation boost transistor gate, the second series boost transistor gate, and the second coupling capacitor lower plate are coupled;

wherein the second series boost transistor source, the first isolation boost transistor gate, the first series boost transistor gate, the third series boost transistor gate, and the first coupling capacitor lower plate are coupled;

wherein the first isolation boost transistor source, first series boost transistor drain, and the third series boost transistor drain are coupled;

wherein the second isolation boost transistor source and the second series boost transistor drain are coupled;

wherein the first isolation boost transistor drain and the second isolation boost transistor drain are coupled to a high voltage control node; and

wherein the first coupling capacitor upper terminal is coupled to a first clock input, and the second coupling capacitor upper terminal is coupled to a second clock input.

2. A high voltage pass gate as in claim 1, further comprising:

first, second, and third discharge transistors;

wherein the first discharge transistor drain is coupled to the second coupling capacitor lower plate, the second discharge transistor drain is coupled to the first coupling capacitor lower plate, and the third discharge transistor drain is coupled to the third series boost transistor source.

3. A high voltage pass gate as in claim 2, further comprising:

first and second regulation transistors;

wherein the first regulation transistor drain is coupled to the first isolation boost transistor source, the second regulation transistor drain is coupled to the second isolation boost transistor source; and

wherein the first regulation transistor gate and source and the second regulation transistor gate and source are coupled to a generator on signal.

4. A high voltage pass gate as in claim 3, further comprising:

one or more pass transistors;

wherein the third series boost transistor source is coupled to the pass transistor gates, the pass transistor drains are coupled to a high voltage generator node, and the pass transistor sources are coupled to a word line.

5. A high voltage pass gate as in claim 2,

wherein a positive supply voltage is coupled to the first, second, and third discharge transistor gates, and a decode input is coupled to the first, second, and third discharge transistor source.

6. A high voltage pass gate as in claim 1,

wherein the plurality of transistors comprise Z-type transistors.

7. A high voltage pass gate as in claim 4,

wherein the pass transistors comprise enhancement transistors.

8. A high voltage pass gate as in claim 7,

wherein the high voltage control node is regulated such that its voltage is at least one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node.

9. A high voltage pass gate as in claim 7,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node plus a predetermined voltage margin.

10. A high voltage pass gate, comprising:

first, second, third, and fourth coupling capacitors each having upper and lower plates;

a plurality of transistors, each transistor having a corresponding gate, source, and drain, wherein the plurality of transistors comprises;

first, second, and third series boost transistors;

first and second isolation boost transistors;

wherein the first series boost transistor source, the second series boost transistor gate, and the fourth coupling capacitor lower plate are coupled;

wherein the second series boost transistor source, the first series boost transistor gate, the third series boost transistor gate, and the second coupling capacitor lower plate are coupled;

wherein the first isolation boost transistor source, the first series boost transistor drain, the third series boost transistor drain, the second isolation boost transistor gate, and the third coupling capacitor lower terminal are coupled;

wherein the second isolation boost transistor source, the second series boost transistor drain, the first isolation boost transistor gate, and the first coupling capacitor lower terminal are coupled;

wherein the first isolation boost transistor drain and the second isolation boost transistor drain are coupled to a high voltage control node; and

wherein the first coupling capacitor upper terminal and second coupling capacitor upper terminal are coupled to a first clock input, and the second coupling capacitor upper terminal and the fourth coupling capacitor upper terminal are coupled to a second clock input.

11. A high voltage pass gate as in claim 10, further comprising:

first, second, and third discharge transistors;

wherein the first discharge transistor drain is coupled to the fourth coupling capacitor lower plate, the second discharge transistor drain is coupled to the second coupling capacitor lower plate, and the third discharge transistor drain is coupled to the third series boost transistor source.

12. A high voltage pass gate as in claim 11, further comprising:

first and second regulation transistors;

wherein the first regulation transistor drain is coupled to the first isolation boost transistor source, the second regulation transistor drain is coupled to the second isolation boost transistor source; and

wherein the first regulation transistor gate and source and the second regulation transistor gate and source are coupled to an intermediate high-voltage generator on signal.

13. A high voltage pass gate as in claim 12, further comprising:

one or more pass transistors;

wherein the third series boost transistor source is coupled to the pass transistor gates, the pass transistor drains are coupled to a high voltage generator node, and the pass transistor sources are coupled to a word line.

14. A high voltage pass gate as in claim 12, further comprising:

first, second, and third series discharge transistors;

wherein the first discharge transistor source is coupled to the first series discharge transistor drain, the second discharge transistor source is coupled to the second series discharge transistor drain, and the third discharge transistor source is coupled to the third series discharge transistor drain;

wherein a positive supply voltage is coupled to the first, second, and third series discharge transistor gates, and a decode input is coupled to the first, second, and third series discharge transistor sources; and

wherein the first, second, and third discharge transistor gates are coupled to the intermediate high-voltage generator on signal.

15. A high voltage pass gate as in claim 10,

wherein the plurality of transistors comprise Z-type transistors.

16. A high voltage pass gate as in claim 10,

wherein the plurality of transistors comprise enhancement transistors.

17. A high voltage pass gate as in claim 13,

wherein the pass transistors comprise enhancement transistors.

18. A high voltage pass gate as in claim 17,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node.

19. A high voltage pass gate as in claim 10,

wherein the first and second isolation boost transistors comprise Z-type transistors;

and

wherein the first, second, and third series boost transistors comprise enhancement transistors.

20. A high voltage pass gate as in claim 17,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node plus a predetermined voltage margin.

21. A high voltage pass gate, comprising:

first, second, third, and fourth coupling capacitors each having upper and lower plates;

a plurality of transistors, each transistor having a corresponding gate, source, and drain, wherein the plurality of transistors comprises;

first, second, and third series boost transistors;

first and second isolation boost transistors;

first and second decoupling boost transistors;

wherein the first series boost transistor source, the second isolation boost transistor gate, the second series boost transistor gate, and the fourth coupling capacitor lower plate are coupled;

wherein the second series boost transistor source, the first isolation boost transistor gate, the first series boost transistor gate, the third series boost transistor gate, and the second coupling capacitor lower plate are coupled;

wherein the first isolation boost transistor source, first series boost transistor drain, the third series boost transistor drain, the second decoupling boost transistor gate, and the third coupling capacitor lower plate are coupled;

wherein the second isolation boost transistor source, the second series boost transistor drain, the first decoupling boost transistor gate, and the first coupling capacitor lower plate are coupled;

wherein the first decoupling boost transistor source and the second isolation boost transistor drain are coupled;

wherein the second decoupling boost transistor source and the second isolation boost transistor drain are coupled;

wherein the first isolation boost transistor drain and the second isolation boost transistor drain are coupled to a high voltage control node; and

wherein the first and second coupling capacitor upper terminals are coupled to a first clock input, and the third and fourth coupling capacitor upper terminals are coupled to a second clock input.

22. A high voltage pass gate as in claim 21, further comprising:

first, second, and third discharge transistors;

wherein the first discharge transistor drain is coupled to the fourth coupling capacitor lower plate, the second discharge transistor drain is coupled to the second coupling capacitor lower plate, and the third discharge transistor drain is coupled to the third series boost transistor source;

wherein the first, second, and third discharge transistor sources are coupled to a decode signal; and

wherein the first, second, and third discharge transistor gates are coupled to a positive supply voltage.

23. A high voltage pass gate as in claim 21, further comprising:

first and second regulation transistors; and

first and second series regulation transistors;

wherein the first regulation transistor drain is coupled to the first isolation boost transistor source, the second regulation transistor drain is coupled to the second isolation boost transistor source;

wherein the first and second regulation transistor gates and the first and second series regulation transistor sources are coupled to a generator on signal;

wherein the first and second series regulation transistor gates are coupled to an inverted decode signal.

24. A high voltage pass gate as in claim 23, further comprising:

one or more pass transistors;

wherein the third series boost transistor source is coupled to the pass transistor gates, the pass transistor drains are coupled to a high voltage generator node, and the pass transistor sources are coupled to a word line.

25. A high voltage pass gate as in claim 23,

wherein the plurality of transistors comprise Z-type transistors.

26. A high voltage pass gate as in claim 23,

wherein the plurality of transistors comprise enhancement transistors.

27. A high voltage pass gate as in claim 24,

wherein the pass transistors comprise enhancement transistors.

28. A high voltage pass gate as in claim 27,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node.

29. A high voltage pass gate as in claim 27,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node plus a predetermined voltage margin.

30. A high voltage pass gate, comprising:

first, second, third, and fourth coupling capacitors each having upper and lower plates;

a plurality of transistors, each transistor having a corresponding gate, source, and drain, wherein the plurality of transistors comprises;

first, second, and third series boost transistors;

first and second isolation boost transistors;

first and second decoupling boost transistors;

wherein the first series boost transistor source, the second isolation boost transistor gate, the second series boost transistor gate, and the fourth coupling capacitor lower plate are coupled;

wherein the second series boost transistor source, the first isolation boost transistor gate, the first series boost transistor gate, the third series boost transistor gate, and the second coupling capacitor lower plate are coupled;

wherein the first isolation boost transistor source, and the first series boost transistor drain, and the third series boost transistor drain are coupled;

wherein the second isolation boost transistor source and the second series boost transistor drain are coupled;

wherein the first decoupling boost transistor source, the first isolation boost transistor drain, and the second decoupling boost transistor gate are coupled;

wherein the second decoupling boost transistor source, the second isolation boost transistor drain, and the first decoupling boost transistor gate are coupled;

wherein the first isolation boost transistor drain and the second isolation boost transistor drain are coupled to a high voltage control node; and

wherein the first and second coupling capacitor upper terminals are coupled to a first clock input, and the third and fourth coupling capacitor upper terminals are coupled to a second clock input.

31. A high voltage pass gate as in claim 30, further comprising:

first and second coupling boost transistors;

wherein the first coupling boost transistor drain is coupled to the first decoupling boost transistor source, the first coupling boost transistor gate is coupled to the second coupling capacitor lower terminal, and the first coupling boost transistor source is coupled to the second series boost transistor drain; and

wherein the second coupling boost transistor drain is coupled to the second decoupling boost transistor source, the second coupling boost transistor gate is coupled to the fourth coupling capacitor lower terminal, and the second coupling boost transistor source is coupled to first series boost transistor drain.

32. A high voltage pass gate as in claim 31, further comprising:

first, second, and third discharge transistors;

first and second intermediate regulation transistors; and

first and second regulation transistors;

wherein the first discharge transistor drain is coupled to the fourth coupling capacitor lower plate, the second discharge transistor drain is coupled to the second coupling capacitor lower plate, and the third discharge transistor drain is coupled to the third series boost transistor source;

wherein the first intermediate regulation transistor drain is coupled to the first isolation boost transistor source, and the second intermediate regulation transistor drain is coupled to the second isolation boost transistor source;

wherein the first regulation transistor drain is coupled to the third coupling capacitor lower plate, and the second regulation transistor drain is coupled to the first decoupling capacitor lower plate;

wherein the first, second, and third discharge transistor gates, the first and second regulation transistor gates and sources, and the first and second intermediate regulation transistor gates are coupled to an intermediate high voltage generator on signal.

33. A high voltage pass gate as in claim 32, further comprising:

first, second, and third series discharge transistors; and

first and second series intermediate regulation transistors;

wherein the first series discharge transistor drain is coupled to the first discharge transistor source, the second series discharge transistor drain is coupled to the second discharge transistor source, and the third series discharge transistor drain is coupled to the third discharge transistor source;

wherein the first series intermediate regulation transistor drain is coupled to the first intermediate regulation transistor source, and the second series intermediate regulation transistor drain is coupled to the second intermediate regulation transistor source;

wherein the first, second, and third series discharge transistor sources are coupled to a decode signal;

wherein the first and second series intermediate regulation transistor gates are coupled to an inverted decode signal; and

wherein the first and second series intermediate regulation transistor sources are coupled to a generator on logic signal.

34. A high voltage pass gate as in claim 33,

wherein the first, second, and third series discharge transistor gates are coupled to a logical nand of the decode signal and the generator on logic signal.

35. A high voltage pass gate as in claim 32, further comprising:

one or more pass transistors;

wherein the third series boost transistor source is coupled to the pass transistor gates, the pass transistor drains are coupled to a high voltage generator node, and the pass transistor sources are coupled to a word line.

36. A high voltage pass gate as in claim 30,

wherein the plurality of transistors comprise Z-type transistors.

37. A high voltage pass gate as in claim 35,

wherein the pass transistors comprise enhancement transistors.

38. A high voltage pass gate as in claim 37,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node.

39. A high voltage pass gate as in claim 30, further comprising:

a coupling boost transistor;

wherein the coupling boost transistor drain is coupled to the second decoupling boost transistor source, the coupling boost transistor gate is coupled to the fourth coupling capacitor lower terminal, and the coupling boost transistor source is coupled to first series boost transistor drain.

40. A high voltage pass gate as in claim 36,

wherein the high voltage control node is regulated such that its voltage is one enhancement transistor threshold voltage higher than a voltage at the high voltage generator node plus a predetermined voltage margin.