Memory system

• US 5,844,841 A
• Filed: 04/18/1997
• Issued: 12/01/1998
• Est. Priority Date: 04/19/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/844,724
• Time in Patent Office: 592 Days
• Field of Search: 365/185.03, 365/185.22, 365/200, 365/168, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.

Claims

1. A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein

said memory cell is operated as an n-level data storing memory cell until the number of times a write-erase sequence has been performed reaches a predetermined number of times, and said memory cell is operated as an m-level data storing memory cell (m is an integer smaller than n) when the number of times the write-erase sequence has been performed has exceeded the predetermined number of times.

2. A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein

said memory cell is operated as an n-level data storing memory cell until the number of times a write-erase sequence has been performed reaches an n-th number of times, said memory cell is operated as an (n-1) level data storing memory cell after the write-erase sequence has been performed the n-th number of times and until the number of times the write-erase sequence has been performed reaches an (n-1)th number of times, and said memory cell is operated as an i-level data storing memory cell (i is an integer equal to or larger than 2) after the write-erase sequence has been performed an (i+1)th number of times and until the number of times the write-erase sequence has been performed reaches an i-th number of times.

3. A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), said memory system further comprising

a level holding portion for storing information of the level of data stored in said memory cell.

4. A memory system comprising a memory portion including memory cells comprising

a first memory cell operating as an n-level data storing memory cell (n is an integer greater than or equal to 3);

and

a second memory cell operating as an m-level data storing memory cell (m is an integer smaller than n), wherein said second memory cell operated as an n-level data storing memory cell until the number of times data was written to or erased from said second memory cell exceeded a predetermined number.

5. A memory system comprising a memory portion including a memory cell for storing p-level data (p is an integer larger than 2), wherein

cycles are repeated, each cycle including a data writing or erasing operation into or from said memory cell and a verify read operation for detecting a state of said memory cell;

the number of the repeated cycles of said writing operation or the erasing operation and the verify read operation is monitored;

a data write voltage to said memory cell in a data write mode or an erase voltage to said memory cell in a data erase mode is increased after the number of the repeated cycles which are performed until data has been successfully written into or erased from said memory cell has reached a predetermined number of times; and

said memory cell is operated as an i-level data storing memory cell (i is an integer smaller than p) when the number of times the data writing operation or the data erasing operation has been performed exceeds a predetermined number of times.

6. A memory system according to claim 5, wherein an initial value of the data write voltage in the repeated cycles to said memory cell in the data write mode or an initial value of the erase voltage in the repeated cycles to said memory cell in the data erase mode is increased after the number of the repeated cycles which are performed until data has been successfully written into or erased from said memory cell has reached the predetermined number of times.

7. A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or greater than 3), wherein

said memory cell is operated as an n-level data storing memory cell until the number of times a writing/erasing operation has been performed reaches a predetermined number, and said memory cell is operated as an m-level data storing memory cell (m is an integer smaller than n) when the number of times the writing/erasing operation has been performed exceeds the predetermined number of times.

8. A memory system according to claim 7, wherein said memory cell is operated as a 2-level data storing memory cell when the number of times the writing/erasing operation has been performed exceeds the predetermined number of times.

9. A memory system according to claim 8, wherein cycles are repeated each of which includes a data writing or erasing operation into or from said memory cell and a verify read operation for detecting a state of said memory cell;

the number of the repeated cycles of the data writing or erasing operation and the verify read operation is monitored; and

a change of the n-level memory mode to the 2-level data memory mode is performed after the number of the repeated cycles has reached a predetermined number of times.

10. A memory system according to claim 7, wherein a change of an n-level data memory mode to an m-level data memory mode is performed in a memory chip unit including said memory portion.

11. A memory system according to claim 7, wherein said memory portion includes a memory cell block including a predetermined number of memory cells, said memory cell block serving as a unit for collectively writing or erasing data, and a change of an n-level data memory mode to an m-level data memory mode is performed in the memory cell block unit.

12. A memory system according to claim 7, wherein data is neither written into said memory cell nor erased from said memory cell after the number of times the writing/erasing operation has been performed reaches a certain number in an m-level data memory mode after a change of an n-level data memory mode to the m-level data memory mode has been performed.

13. A memory system according to claim 7, wherein said memory cell is not used after the number of times the writing/erasing operation has been performed reaches a certain number in an m-level data memory mode after change of an n-level data memory mode to the m-level data memory mode has been performed.

14. A memory system according to claim 7, wherein

cycles are repeated, each cycle including a data writing or erasing operation into or from said memory cell and a verify read operation for detecting a state of said memory cell;

the number of the repeated cycles of the data writing or erasing operation and the verify read operation is monitored; and

a change of an n-level data memory mode to an m-level data memory mode is performed after the number of the repeated cycles has reached a predetermined number.

15. A memory system according to claim 7, wherein a data write voltage to said memory cell in a data write mode or an erase voltage to said memory cell in a data erase mode is increased when said memory cell is operated as the m-level data storing memory cell after the number of times the write/erase operation has been performed has exceeded the predetermined number of times.

16. A memory system according to claim 7, wherein a width of a data write pulse to said memory cell in a data write mode or a width of a data erase pulse to said memory cell in a data erase mode is increased when said memory cell is operated as the m-level data storing memory cell after the number of times the write/erase operation has been performed has exceeded the predetermined number of times.

17. A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein

said memory cell is operated as an n-level data storing memory cell until the number of times a writing/erasing operation has been performed reaches an n-th number of times, said memory cell is operated as an (n-1) level data storing memory cell after the writing/erasing operation has been performed the n-th number of times and until the number of times the writing/erasing operation has been performed reaches an (n-1)th number of times, and said memory cell is operated as an i-level data storing memory cell (i is an integer equal to or greater than 2) after the writing/erasing operation has been performed an (i+1)th number of times and until the number of times the writing/erasing operation has been performed reaches an i-th number of times.

18. A memory system according to claim 17, wherein a change of an n-level data memory mode to an (n-1) level data memory mode or a change of an (i+1) level data memory mode to an i-level data memory mode is performed in a memory chip unit including said memory portion.

19. A memory system according to claim 17, wherein said memory portion includes a memory cell block including a predetermined number of memory cells, said memory cell block serving as a unit for collectively writing or erasing data, and a change of an n-level data memory mode to an (n-1) level data memory mode or a change of an (i+1) level data memory mode to an i-level data memory mode is performed in the memory cell block unit.

20. A memory system according to claim 17, wherein data is neither written into said memory cell nor erased from said memory cell after the number of times the writing/erasing operation has been performed reaches a certain number in an (n-1) level data memory mode after a change of an n-level data memory mode to the (n-1) level data memory mode has been performed or after the number of times the writing/erasing operation has been performed reaches a certain number in an i-level data memory mode after a change of an (i+1) level data memory mode to the i-level data memory mode has been performed.

21. A memory system according to claim 17, wherein said memory cell is not used after the number of times the writing/erasing operation has been performed reaches a certain number in an (n-1) level data memory mode after change of an n-level data memory mode to the (n-1) level data memory mode has been performed or after the number of times the writing/erasing operation has been performed reaches a certain number in an i-level data memory mode after change of an (i+1) level data memory mode to the i-level data memory mode has been performed.

22. A memory system according to claim 17, wherein

cycles are repeated, each cycle including a data writing or erasing operation into or from said memory cell and a verify read operation for detecting a state of said memory cell;

the number of the repeated cycles of the data writing or erasing operation and the verify read operation is monitored; and

a change of an n-level data memory mode to an (n-1) level data memory mode or a change of an (i+1) level data memory mode to an i-level data memory mode is performed after the number of the repeated cycles has reached a predetermined number.

23. A memory system according to claim 17, wherein a data writing voltage to said memory cell in a data write mode or a data erase voltage in a data erase mode is increased when said memory cell is operated as the (n-1) level data storing memory cell after the number of times the write/erase operation has been performed has exceeded the n-th number of times or when said memory cell is operated as the i-level data storing memory cell after the number of times the write/erase operation has been performed has exceeded the (i+1)th number of times.

24. A memory system according to claim 17, wherein a width of a data write pulse to said memory cell in a data write mode or a width of a data erase pulse to said memory cell in a data erase mode is increased when said memory cell is operated as the (n-1) level data storing memory cell after the number of times the write/erase operation has been performed has exceeded the n-th number of times or when said memory cell is operated as the i-level data string memory cell after the number of times the write/erase operation has been performed has exceeded the (i+1)th number of times.

25. A memory system comprising memory cells, each memory cell capable of storing any one of "n" threshold levels, the threshold levels designating respective states corresponding to the storage of "n"-level data, wherein "n" is an integer equal to or larger than 3 and "n" is decreased for said memory cells when the number of times data is written to or erased from said memory cells exceeds a predetermined number.