Test circuit and method for refresh and descrambling in an integrated memory circuit

• US 5,844,914 A
• Filed: 05/02/1997
• Issued: 12/01/1998
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Heon-Cheol, Jun, Hong-Sin, Cho, Chang-Hyun
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/850,807
• Time in Patent Office: 578 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.3, 371/21.6, 711/170, 711/211, 711/212, 395/307, 395/310
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

Abstract

A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

Claims

1. A semiconductor integrated circuit having a test circuit section and a memory circuit section, the semiconductor integrated circuit comprising:

an address generating circuit configured to generate a testing address for testing said memory circuit section;

a data generating circuit configured to generate test data for testing said memory circuit section;

a refresh address generating circuit configured to generate a refresh address for refreshing said memory circuit section when the generated address matches a refresh point address;

an address multiplexer configured to select one of the test address and the refresh address responsive to an address control signal; and

a built-in self test control circuit configured to execute a predetermined test algorithm and control said address generating circuit and said data generating circuit responsive to the test algorithm, and the control circuit being further configured to determine whether a time period for accessing a cell of said memory circuit section is greater than a predetermined refresh time required for the memory circuit section and to calculate a corresponding refresh point address, and the control circuit being still further configured to compare the test address to the refresh point address and disable said address generating circuit and enable said refresh address generating circuit when the test address matches the refresh point address, and the control circuit being yet still further configured to provide the address control signal to the address multiplexer such that the test address is output to the memory circuit section when said address generating circuit is enabled and the refresh address is output to the memory circuit section when said refresh address generating circuit is enabled.

2. A semiconductor integrated circuit as claimed in claim 1, wherein said test circuit section performs a march test algorithm and the number of refresh cycles corresponds to a time period for accessing a given address.

3. A semiconductor integrated circuit as claimed in claim 1, wherein said memory circuit section comprises an embedded dynamic random access memory.

4. A test method for a semiconductor integrated circuit having a test circuit section and a memory circuit section, the test method comprising the steps of:

calculating a refresh point address based upon a time period required to complete a predetermined test algorithm on the memory circuit section and a predetermined refresh time required to maintain data stored in the memory circuit section;

generating a test address and test data for testing a cell in the memory circuit section;

comparing the test address with the refresh point address;

holding the test address when the test address matches the refresh point address;

performing a refresh operation to refresh the data stored in memory circuit section beginning with the refresh point address when the test address matches the refresh point address; and

resuming the test algorithm at the test address after termination of the refresh operation.

5. The method of claim 4, wherein the step of generating a test address and test data for testing a cell in the memory circuit section further includes the steps of:

descrambling the test address before inputting the test address into the memory circuit section; and

descrambling the test data before inputting the test data into the memory circuit section.

6. A test method for a semiconductor integrated circuit having a test circuit section and a memory circuit section, wherein the memory circuit section includes logic for scrambling an address and a data signal input to the memory circuit section, the test method comprising the steps of:

generating a test address and test data for testing a cell in the memory circuit section;

descrambling the test address before inputting the test address into the memory circuit section; and

descrambling the test data before inputting the test data into the memory circuit section.

7. A semiconductor integrated circuit, the circuit comprising:

a memory circuit section having an address scrambling circuit adapted to scramble an input address signal, a data scrambling circuit adapted to scramble an input data signal, and a memory cell array adapted to store scrambled data output from the data scrambling circuit in cells corresponding to scrambled addresses output from the address scrambling circuit; and

a test circuit section coupled to the memory circuit section and further comprising;

an address counting circuit adapted to sequentially count a test address for testing said memory circuit section;

an address descrambling circuit adapted to descramble the test address output from the address counting circuit to produce a descrambled test address which is output as the input address signal to the address scrambling circuit of the memory circuit section such that the test address matches the address of the memory cell array;

a data generating circuit adapted to generate test data for testing the memory circuit section;

a data descrambling circuit adapted to descramble the test data output from the data generating circuit to produce the input data signal to the memory circuit section such that the test data matches the data stored in the memory cell array for a given test address; and

a built-in self test (BIST) control circuit being enabled by an external test enable signal, and operating in response to an external clock signal, wherein the BIST control circuit executes a test algorithm on the memory circuit section by controlling said address counting circuit and said data generating circuit in accordance with the test algorithm.

8. The semiconductor integrated circuit of claim 7, wherein the test circuit section includes:

a refresh address generating circuit configured to generate a refresh address for refreshing said memory circuit section when the generated address matches a refresh point address;

an address multiplexer configured to select one of the test address and the refresh address responsive to an address control signal generated by the BIST control circuit; and

wherein the BIST control circuit is further configured to determine whether a time period for accessing a cell of said memory circuit section is greater than a predetermined refresh time required for the memory circuit section and to calculate the refresh point address based upon the test algorithm and the predetermined refresh time, and the control circuit being still further configured to compare the test address to the refresh point address and disable said address generating circuit and enable said refresh address generating circuit when the test address matches the refresh point address, and the control circuit being yet still further configured to provide the address control signal to the address multiplexer such that the test address is output to the memory circuit section when said address generating circuit is enabled and the refresh address is output to the memory circuit section when said refresh address generating circuit is enabled.