Data-input device for generating test signals on bit and bit-complement lines

• US 5,845,059 A
• Filed: 01/19/1996
• Issued: 12/01/1998
• Est. Priority Date: 01/19/1996
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): PALYS, JOSEPH E
• Application Number:
  US08/588,762
• Time in Patent Office: 1,047 Days
• Field of Search: 371/21.1, 371/22.5, 371/63, 371/67.1, 371/22.6, 371/22.4, 371/21.5, 371/2.6, 371/28, 371/49.3, 371/2.1, 371/2.2, 371/27.1, 395/183.03, 395/183.18, 365/201
• US Class Current: 714/27
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A data input circuit is used in a memory device having an externally accessible data pin. The data input circuit includes first and second data output terminals and a test terminal that receives a test signal. A data converter is coupled to the first and second data output terminals and to the test terminal, and places complementary signal levels on the first and second data output terminals when the test signal is absent from the test terminal, and places a same signal level on both the first and second data output terminals when the test signal is present on the test terminal. The data input circuit may include an input terminal that is coupled to the data pin, where the data converter is coupled to the input terminal. When the test signal is present on the test terminal, the data converter places on the first data output terminal a signal level equal to a signal level that occupies the data pin during a first time period, and places on the second data output terminal a signal level equal to a signal level that occupies the data input terminal during a second time period.

Claims

1. A data input circuit for use in a memory device having a data pin, said circuit comprising:

first and second data output terminals;

a test terminal operable to receive a test signal;

a data converter coupled to said first and second data output terminals and said test terminal, said data converter operable to place complementary signal levels on said first and second data output terminals when said test signal is absent from said test terminal;

an input terminal coupled to said data pin;

a mode terminal operable to receive a mode signal that toggles from first state to a second state at a desired toggle time; and

said data converter coupled to said input and mode terminals, said data converter operable, after said toggle time and when said test signal is present on said test terminal,

to place a first signal level on both said first and second data output terminals when a first data value is present on said data pin both before and after said toggle time,

to place said first signal level on said first data output terminal and a second signal level on said second data output terminal when said first data value is present on said data pin before said toggle time and a second data value is present on said data pin after said toggle time,

to place said second signal level on said first data output terminal and said first signal level on said second data output terminal when said second data value is present on said data pin before said toggle time and said first data value is present on said data pin after said toggle time, and

to place said second signal level on both said first and second data output terminals when said second data value is present on said data pin both before and after said toggle time.

2. The data input circuit of claim 1 wherein:

said first signal level, first state, and first data value equal a logic zero; and

said second signal level, second state, and second data value, equal a logic one.

3. A data input circuit for use in a memory device having a data pin, said circuit comprising:

first and second data output terminals;

a test terminal operable to receive a test signal;

a data converter coupled to said first and second data output terminals and said test terminal, said data converter operable to place complementary signal levels on said first and second data output terminals when said test signal is absent from said test terminal;

an input terminal coupled to said data pin;

a mode terminal operable to receive a mode signal that toggles from first state to a second state at a desired toggle time; and

said data converter coupled to said input and mode terminals, said data converter operable, when said test signal is present on said test terminal,

to place on said first data output terminal a signal level equal to a signal level that is present on said data pin when said mode signal is in said first state, and

to place on said second data output terminal a signal level equal to a signal level that is present on said data pin when said mode signal is in said second state.

4. A data input circuit for writing data to a memory cell of a memory device having an externally accessible data pin that is operable to receive an input data signal having a value, said memory cell having first and second complementary data terminals, said circuit comprising:

first and second data output terminals respectively coupled to said first and second complementary data terminals of said memory cell;

a test terminal operable to receive a test signal;

a data converter coupled to said first and second data output terminals, said externally accessible data pin, and said test terminal, said data converter operable to place write data signals having complementary values on said first and second complementary data terminals, respectively, of said memory cell when said test signal is absent from said test terminal, said data converter operable to place write data signals having a same value on said first and second complementary data terminals, respectively, when said test signal is present on said test terminal, said same value depending on said value of said input data signal.

5. A data input circuit, comprising:

a data input terminal;

a test-mode terminal operable to receive a test-mode signal that has active and inactive states;

first and second complementary data output terminals;

a first driver having an input terminal coupled to said data input terminal and an output terminal coupled to said first complementary data output terminal;

a second driver having a first and second input terminals and having an output terminal coupled to said second complementary data output terminal;

a switch having a control terminal, a first switch terminal coupled to said data input terminal, and a second switch terminal coupled to said first input terminal of said second driver; and

a test circuit having a first input terminal coupled to said test-mode terminal, a second input terminal coupled to said data input terminal, a first output terminal coupled to said second input terminal of said second driver, and a second output terminal coupled to said control terminal of said switch.

6. The data input circuit of claim 5, further comprising a memory circuit coupled between said data input terminal and both said first driver and said switch, said memory circuit having a mode terminal, an input terminal coupled to said data input terminal, and an output terminal coupled to said input terminal of said first driver and said first switch terminal of said switch.

7. The data input circuit of claim 5, further comprising:

a memory circuit coupled between said data input terminal and both said first driver and said switch, said memory circuit having a mode terminal, an input terminal coupled to said data input terminal, and an output terminal coupled to said input terminal of said first driver and said first switch terminal of said switch; and

said test circuit having a third input terminal coupled to said output terminal of said memory circuit.

8. A memory device, comprising:

a write power line and a write-complement power line;

a plurality of data terminals;

a plurality of memory cells each having bit and bit-complement terminals;

a plurality of bit column lines each coupled to said bit terminal of an associated memory cell;

a plurality of bit-complement column lines each coupled to said bit-complement terminal of an associated memory cell;

a plurality of data input circuits each having an input terminal coupled to an associated one of said data terminals, data and data-complement output terminals, and a test terminal, each of said data input circuits operable to place a first signal level on both said data and data-complement output terminals when a test signal is applied to said test terminal; and

a plurality of write driver circuits each having write power and write-complement power terminals respectively coupled to said write and write-complement power lines, data and data-complement input terminals coupled to said data and data-complement output terminals, and write and write-complement terminals respectively coupled to said bit and bit-complement column lines of an associated memory cell, each write driver circuit operable to couple said write terminal to said write power terminal when said data input terminal carries said first signal level and operable to couple said write-complement terminal to said write-complement power terminal when said data-complement input terminal carries said first signal level.

9. The memory device of claim 8, further comprising a plurality of pass gates each coupled between one of said bit and bit-complement column lines and a corresponding one of said write and write-complement terminals, each pass gate operable to couple said one of said bit and bit-complement column lines that is coupled to an addressed one of said memory cells to said corresponding one of said write and write-complement terminals.

10. A method for testing a memory cell having bit and bit-complement terminals respectively coupled to first and second data output terminals of a data input circuit having a single data input terminal comprising:

placing a first signal value on both said first and second data output terminals when a first signal level occupies said data input terminal during both a first and a second time period;

placing said first signal value on said first data output terminal and a second signal value on said second data output terminal when said first signal level occupies said data input terminal during said first time period and a second signal level occupies said data input terminal during said second time period;

placing said second signal value on said first data output terminal and said first signal value on said second data output terminal when said second signal level occupies said data input terminal during said first time period and said first signal level occupies said data input terminal during said second time period; and

placing said second signal value on both said first and second data output terminals when said second signal level occupies said data input terminal during both said first and second time periods.

11. A method for testing a memory cell having bit and bit-complement terminals respectively coupled to first and second data output terminals of a data input circuit having a single data input terminal comprising:

placing on said first data output terminal a signal value equal to a signal level that occupies said data input terminal during a first time period; and

placing on said second data output terminal a signal value equal to a signal level that occupies said data input terminal during a second time period.

12. A computer system, comprising:

a data input device;

a data output device;

an address bus;

a data bus having one or more data lines; and

computing circuitry coupled to said data input device, said data output device, said address bus, and said data bus, said computing circuitry including a memory device that includes,

a write power line and a write-complement power line,

a plurality of data terminals each coupled to one of said data lines,

a plurality of memory cells each having bit and bit-complement terminals,

a plurality of bit column lines each coupled to said bit terminal of an associated memory cell,

a plurality of bit-complement column lines each coupled to said bit-complement terminal of an associated memory cell,

a plurality of data input circuits each having an input terminal coupled to an associated one of said data terminals, data and data-complement output terminals, and a test terminal, each of said data input circuits operable to place first signal level on both said data and data-complement output terminals when a test signal is applied to said test terminal, and

a plurality of write driver circuits each having write power and write-complement power terminals respectively coupled to said write and write-complement power lines, data and data-complement input terminals coupled to said data and data-complement output terminals, and write and write-complement terminals respectively coupled to said bit and bit-complement column lines of an associated memory cell, each write driver circuit operable to couple said write terminal to said write power terminal when said data input terminal carries said first signal level and operable to couple said write-complement terminal to said write-complement power terminal when said data-complement input terminal carries said first signal level.

13. The computer system of claim 12 wherein said memory device further comprises:

an address decoder coupled to said address bus;

a plurality of pass gates each having a control input coupled to said address decoder and each coupled between one of said bit and bit-complement column lines and a corresponding one of said write and write-complement terminals, each pass gate operable to couple said one of said bit and bit-complement column lines that is coupled to an addressed one of said memory cells to said corresponding one of said write and write-complement terminals.

14. A data input circuit for use in a memory device having an externally accessible data terminal, said circuit comprising:

an input terminal coupled to said externally accessible data terminal;

first and second data output terminals;

a test terminal operable to receive a test signal;

a clock terminal operable to receive a clock signal;

a latch circuit coupled to said input terminal, said clock terminal, and said first and second data output terminals, said latch circuit operable to receive a first data signal from said input terminal when said clock has a first state, and to store said first data signal and provide said first data signal to said first output terminal when said clock signal has a second state;

a test circuit coupled to said input terminal, said test terminal, said second output terminal, and said latch circuit, said test circuit operable to receive a second data signal from said input terminal and said first data signal from said latch circuit when said clock signal has said second state and to generate from said first and second data signals a third data signal on said second output terminal.

15. The data input circuit of claim 14 wherein said test circuit is operable to generate said third data signal such that said first and third data signals together form up to four binary values.

16. A data input circuit for use in a memory device having a data terminal that is operatively coupled to receive a first test signal, said circuit comprising:

a pair of output terminals;

a test terminal operable to receive a second test signal;

a mode terminal operable to receive a clock signal having first and second clock periods;

a data converter coupled to said data terminal, said output terminals, said test terminal, and said mode terminal, said data converter operable to drive complementary output data signals onto said respective output terminals when said second test signal has an inactive level, said data converter operable, when said second test signal has an active level,

to drive a first logic level onto both of said output terminals when said first test signal has a second logic level during both of said clock periods,

to drive different logic levels onto said respective output terminals when said first test signal has different logic levels during said respective clock periods, and

to drive a third logic level onto both of said output terminals when said first test signal has a fourth logic level during both of said clock periods.

17. The circuit of claim 16 wherein the first and second logic levels are equal and the third and fourth logic levels are equal.

18. A method for testing a memory cell have bit and bit-complement terminals that are respectively coupled to a pair of data output terminals of a data input circuit having a data input terminal, the method comprising:

during a write mode, placing complementary logic levels on said respective output terminals; and

during a test mode,

driving a first logic level onto both of said output terminals when a test signal on said data input terminal has a second logic level during both of two consecutive clock periods,

driving different logic levels onto said respective output terminals when said test signal has different logic levels during said respective clock periods, and

driving a third logic level onto both of said output terminals when said test signal has a fourth logic level during both of said clock periods.

19. The method of claim 18 wherein the first and second logic levels are equal and the third and fourth logic levels are equal.