Method and apparatus for parallel and pipelining transference of data between integrated circuits using a common macro interface

• US 5,845,072 A
• Filed: 05/05/1997
• Issued: 12/01/1998
• Est. Priority Date: 11/10/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Johnson, Mark C., Ho, Wen-Jei, Finney, Damon W., Lang, Donald J.
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/850,284
• Time in Patent Office: 575 Days
• Field of Search: 395/200.38, 395/200.47, 395/200.48, 395/200.53, 395/200.54, 395/200.55, 395/200.06, 395/200.68, 395/200.8, 395/200.79, 370/466, 370/463, 370/359
• US Class Current: 709/208
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Claims

1. A system for parallel and pipelining transference of data between a plurality of integrated circuits, each of the plurality of integrated circuits having at least one slave and master macro for generating and processing requests, the system comprising:

a unique communication network disposed within each of the integrated circuits for providing parallel and pipelining data transference between the slave and master macros; and

a common protocol interface disposed within each of the integrated circuits for providing a common communication protocol, for requesting and acknowledging data and request transfers between the slave and master macros, each common protocol interface being disposed between the unique communication network and a respective one of the slave and master macros within the at least one of the integrated circuit.

2. The system of claim 1 further comprising an arbiter disposed between the common protocol interface and the slave macro of at least one of the integrated circuits to prevent traffic collisions and locking of the network.

3. The system of claim 1 wherein at least one of the common protocol interfaces uses very high speed integrated circuit (VHSIC) hardware design language.

4. The system of claim 1 wherein the common protocol interfaces and the unique communication networks cooperate to enable macro design to be shared among integrated circuit designers and to facilitate movement of macros from one integrated circuit to another integrated circuit without requiring complete system modifications.

5. The system of claim 1, wherein the common communication protocol comprises:

a first signal for initiating a request by one of the master macros to one of the slave macros;

a second signal provided by the one slave macro for acknowledging the request by the one master macro;

an operation signal provided by the one master macro for indicating whether the request is for sending data to the one slave macro or for obtaining data from the one slave macro; and

a data acknowledgment signal for indicating that the one slave macro received the data sent by the one master macro when the operation signal indicates the request is for sending data to the one slave macro and for indicating that the one slave macro is ready to transmit the requested data to the one master macro when the operation signal indicates the request is for obtaining data.

6. The system of claim 5 further comprising an arbiter disposed in front of the one of the slave macros to prevent traffic collisions and locking of the network.

7. The system of claim 6 wherein at least one of the common network interfaces uses very high speed integrated circuit (VHSIC) hardware design language.

8. A high-end parallel disk control system, comprising:

a memory interface adapter coupled to and transferring data between a processor bus, an input/output port control register, dynamic memory, and a control bus;

a processor coupled to the processor bus;

a buffer interface adapter coupled to the control bus, and the input/output port control register;

a link interface adapter and a system adapter coupled to the control bus, the link interface adapter for communicating with a disk drive system and the system adapter coupled to a communication link;

a data bus disposed between the link interface adapter and the buffer interface adapter for facilitating the transference of data to and from the disk drive system; and

the memory interface adapter, buffer interface adapter, link interface adapter and system adapter having slave and master macros for controlling and processing communications, the processing of communications being accomplished over a unique communication freeway disposed within each of the memory interface adapter, buffer interface adapter, link interface adapter and system adapter for providing parallel and pipelining processes, and a common macro interface providing a common communication protocol for requesting and acknowledging data and request transfers between the slave and master macros.

9. The disk control system of claim 8 wherein each of the common macro interface is disposed between its respective unique communication freeway and the slave and master macros.

10. The system of claim 8 further comprising an arbiter disposed between at least one of the common macro interfaces and at least one of the slave macros to prevent traffic collisions and locking of the freeway.

11. The system of claim 8 wherein at least one of the common macro interfaces uses very high speed integrated circuit (VHSIC) hardware design language.

12. The system of claim 8, wherein the common communication protocol comprises:

a first signal for initiating a request by one of the master macros to one of the slave macros;

a second signal provided by the one slave macro for acknowledging the request by the one master macro;

an operation signal provided by the one master macro for indicating whether the request is for sending data to the one slave macro or for obtaining data from the one slave macro; and

a data acknowledgment signal for indicating that the one slave macro received the data sent by the one master macro when the operation signal indicates the request is for sending data to the one slave macro and for indicating that the one slave macro is ready to transmit the requested data to the one master macro when the operation signal indicates the request is for obtaining data.

13. The system of claim 12 further comprising an arbiter disposed in front of at least one of the slave macros to prevent traffic collisions and locking of the freeway.

14. The system of claim 13 wherein at least one of the common macro interfaces uses very high speed integrated circuit (VHSIC) hardware design language.

15. The system of claim 8 wherein the common macro interfaces and the unique communication freeways cooperate to facilitate sharing and movement of macros between two or more of the memory interface adapter, buffer interface adapter, link interface adapter, and system adapter without requiring complete system modifications.

16. A system for parallel and pipelining transference of data between a plurality of integrated circuits, each of the plurality of integrated circuits having one or more slave and master macros for generating and processing requests, the system comprising:

a unique communication network disposed within at least one of the integrated circuits for providing parallel and pipelining processes; and

a common protocol interface disposed between the unique communication network and a respective one slave macro and a respective one master macro within the at least one of the integrated circuits, for providing a common communication protocol for requesting and acknowledging data and request transfers between the slave and master macros; and

an arbiter disposed between the common macro interface and the respective one slave macro to prevent traffic collisions and locking of the network.

17. The system of claim 16 wherein the common communication protocol comprises a first signal for initiating a request by the respective one master macro to the respective one slave macro, a second signal provided by the respective one slave macro for acknowledging the request by the respective one master macro, an operation signal provided by the respective one master macro for indicating whether the request is for sending data to the slave or for obtaining data from the respective one slave macro, and a data acknowledgment signal for indicating that the respective one slave macro received the data sent by the respective one master macro when the operation signal indicates the request is for sending data to the respective one slave macro and for indicating that the respective one slave macro is ready to transmit the requested data to the respective one master macro when the operation signal indicates the request is for obtaining data.

18. The system of claim 17 wherein the common macro interface and the unique communication freeway cooperate to enable macro design to be shared among integrated circuit designers and to facilitate movement of macros from between integrated circuits without requiring complete system modifications.

19. A method for parallel and pipelining transference of data between a plurality of integrated circuits each having one or more master and slave macros for processing data, the method comprising the steps of:

providing a unique communication network within each of the integrated circuits;

sending a request to a desired one of the slave macros from a particular one of the master macros;

sending an address of the desired slave macro onto at least one of the communication networks;

designating whether the request was a read operation or a write operation;

routing the request to the address of the desired slave macro by one or more of the communication networks;

providing a request acknowledgment signal in response to the desired slave macro receiving the request from the particular master macro; and

providing a data acknowledgment signal from the desired slave macro, the data acknowledgment signal indicating that the data is ready if the operation was a read operation or that the desired slave macro received the data if the operation was a write operation.