Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache

• US 5,845,101 A
• Filed: 05/13/1997
• Issued: 12/01/1998
• Est. Priority Date: 05/13/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pedneau, Mike, Gavin, Matt T., Johnson, William M., Tran, Thang M.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/855,099
• Time in Patent Office: 567 Days
• Field of Search: 395/383, 395/389, 395/584, 395/585, 395/352, 711/125
• US Class Current: 712/207
• CPC Class Codes: G06F 9/30152 Determining start or end of instruction; determining instruction length
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding

Abstract

A microprocessor is configured to speculatively fetch cache lines of instruction bytes prior to actually detecting a cache miss for the cache lines of instruction bytes. The bytes transferred from an external main memory subsystem are stored into one of several prefetch buffers. Subsequently, instruction fetches may be detected which hit the prefetch buffers. Furthermore, predecode data may be generated for the instruction bytes stored in the prefetch buffers. When a fetch hit in the prefetch buffers is detected, predecode data may be available for the instructions being fetched. The prefetch buffers may each comprise an address prefetch buffer included within an external interface unit and an instruction data prefetch buffer included within a prefetch/predecode unit. The external interface unit maintains the addresses of cache lines assigned to the prefetch buffers in the address prefetch buffers. Both the linear address and the physical address of each cache line is maintained. The prefetch/predecode unit receives instruction bytes directly from the external interface and stores the instruction bytes in the corresponding instruction data prefetch buffer.

Claims

1. A method for prefetching, comprising:

storing an address which misses an instruction cache in an address buffer;

initiating an external request for instruction bytes stored at said address;

receiving said instruction bytes into an instruction data buffer;

predecoding said instruction bytes; and

retaining said instruction bytes in said instruction data buffer until completion of said predecoding, even if said predecoding is interrupted.

2. The method as recited in claim 1 wherein said predecoding comprises:

predecoding a first portion of said instruction bytes;

storing an indication of a last one of said first portion of said instruction bytes;

predecoding another set of instruction bytes; and

predecoding a remaining portion of said instruction bytes.

3. The method as recited in claim 2 wherein said predecoding a remaining portion comprises checking said indication to determine a boundary between said first portion of said instruction bytes and said remaining portion of said instruction bytes.

4. The method as recited in claim 1 further comprising discarding said instruction bytes if other instruction bytes are requested from external memory and said instruction bytes are less recent than the additional instruction bytes stored in said instruction data buffer.

5. The method as recited in claim 1 further comprising receiving a fetch address being concurrently searched within said instruction cache.

6. The method as recited in claim 5 further comprising comparing said fetch address to said address.

7. An instruction buffer for storing instructions prior to their storage in an instruction cache of a microprocessor, comprising:

an address buffer configured to store an address corresponding to a plurality of instruction bytes;

an instruction data buffer configured to store said plurality of instruction bytes, wherein said instruction data buffer is coupled to receive said plurality of instruction bytes from a source external to said microprocessor;

a control unit coupled to said instruction data buffer, wherein said control unit is configured to retain said plurality of instruction bytes within said instruction data buffer if an instruction fetching mechanism within said microprocessor initiates an instruction fetch for a second address dissimilar from said address stored in said address buffer; and

a second control unit coupled to said address buffer, wherein said second control unit is coupled to receive a fetch address from said instruction cache, and wherein said instruction cache is concurrently searching for instruction bytes corresponding to said fetch address.

8. The instruction buffer as recited in claim 7 further comprising a predecode data buffer configured to store predecode data corresponding to said plurality of instruction bytes, wherein said predecode data is generated by a predecoder within said microprocessor.

9. The instruction buffer as recited in claim 8 wherein said predecode data buffer additionally stores an indication of which one of said plurality of instruction bytes is next to be predecoded by said predecoder.

10. The instruction buffer as recited in claim 9 wherein said indication is used by said predecoder to continue predecoding said plurality of instruction bytes after said predecoder is interrupted to predecode another plurality of instruction bytes.

11. The instruction buffer as recited in claim 8 wherein said control unit is further configured to transmit said plurality of instruction bytes and said predecode data to said instruction cache for storage.

12. The instruction buffer as recited in claim 11 wherein said control unit is further configured to discard said plurality of instruction bytes from said instruction data buffer upon transmittal to said instruction cache.

13. The instruction buffer as recited in claim 12 wherein said address buffer discards said address concurrent with discard of said plurality of instruction bytes.

14. The instruction buffer as recited in claim 7 wherein said second control unit is configured to compare said fetch address to said address, and wherein said second control unit is further configured to convey a buffer hit signal to said control unit in response to said comparison.

15. The instruction buffer as recited in claim 14 wherein said control unit is configured to convey said plurality of instruction bytes from said instruction data buffer to an instruction processing pipeline of said microprocessor upon receipt of an asserted buffer hit signal, and further configured to convey said plurality of instruction bytes from said instruction data buffer to said instruction cache for storage therein upon receipt of an asserted buffer hit signal.

16. A microprocessor comprising:

an instruction cache configured to store instructions;

a prefetch/predecode unit coupled to receive a plurality of instruction bytes from an external source in response to a fetch miss in said instruction cache, wherein said prefetch/predecode unit is configured to retain said plurality of instruction bytes if said instruction cache fetches an address indicative of another plurality of instruction bytes; and

an external interface unit coupled to said instruction cache and said prefetch/predecode unit, wherein said external interface unit is configured to store an address corresponding to said plurality of instruction bytes and to compare said address to a fetch address being concurrently searched within said instruction cache, and wherein said prefetch/predecode unit conveys said plurality of instruction bytes to an instruction processing pipeline of said microprocessor if said address matches said fetch address.

17. The microprocessor as recited in claim 16 wherein said prefetch/predecode unit predecodes said plurality of instruction bytes, and wherein said plurality of instruction bytes are stored into said instruction cache upon completion of the predecoding.

18. The microprocessor as recited in claim 17 wherein said prefetch/predecode unit is further configured to convey said plurality of instruction bytes to said instruction cache for storage upon detection of said address matching said fetch address.

19. The microprocessor as recited in claim 18 wherein said prefetch/predecode unit is configured to retain said plurality of instruction bytes if one or more of said plurality of instruction bytes are not valid upon conveying said plurality of instruction bytes to said instruction cache for storage.