Digital processor for simulating operation of a parallel processing array

• US 5,845,123 A
• Filed: 02/12/1993
• Issued: 12/01/1998
• Est. Priority Date: 08/16/1990
• Status: Expired due to Term

• Current Assignee: Xylon LLC (Intellectual Ventures LLC)
• Original Assignee: The secretary of state for defence in her Britannic Majesty's Government of the United Kingdom of Great Britain And Northern Ireland
• Inventors: Johnson, Martin, Jones, Robin, Broomhead, David S.
• Primary Examiner(s): Treat, William M.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US07/969,177
• Time in Patent Office: 2,118 Days
• Field of Search: 395/800, 395/377, 364/229.2, 364/231.9
• US Class Current: 712/201
• CPC Class Codes: G06F 15/8046 Systolic arrays

Abstract

A digital processor for simulating operation of a parallel processing array incorporates digital processing units (P₁ to P₈) communicating data to one another via addresses in memories (M₀ to M₈) and registers (R₁₁ to R₄₁). Each processing unit (e.g. P₁) is programmed to input data and execute a computation involving updating of a stored coefficient followed by data output. Each computation involves use of a respective set of data addresses for data input and output, and each processing unit (e.g. P₁) is programmed with a list of such sets employed in succession by that unit. On reaching the end of its list, the processing unit (e.g. P₁) repeats it. Each address set is associated with a conceptual internal cell location in the simulated array (10), and each list is associated with a respective sub-array of the simulated array (10). Data is input cyclically to the processor (40) via input/output ports (I/O₅ to I/O₈) of some of the processing units (P₅ to P₈). Each processing unit (e.g. P₁) executes its list of address sets within a cycle at a rate of one address set per subcycle. At the end of its list, each of the processing units (P₁ to P₈) has executed the functions associated with a conceptual respective sub-array of simulated cells (12), and the processor (40) as a whole has simulated operation of one cycle of a systolic array (10). Repeating the address set lists with further processor input provides successive simulated array cycles.

Claims

1. A digital data processor for simulating operation of a parallel processing array, the processor including an assembly of digital processing devices connected to data storing means, wherein:

(a) each processing device is programmed to implement a respective list of sets of storing means data addresses;

(b) each address set contains input data addresses and output data addresses said input data addresses are different from said output data addresses in each address set, and each address set corresponds to data input/output functions of a respective simulated array cell;

(c) each list of address sets corresponds to a respective sub-array of cells of the simulated array, and each such list contains pairs of successive address sets in which the leading address sets have input data addresses which are the same as output data addresses of respective successive address sets, each list being arranged to provide for operations associated with simulated cells to be executed in reverse order to that corresponding to data flow through the simulated array; and

(d) each processing device is programmed to employ a respective first address set from said respective list to read input data from input data addresses in said respective first address set and to write output data to output data addresses in said respective first address set, the output data being generated in accordance with a computational function, to employ subsequent address sets in said respective lists in succession in a like manner until the list is complete, and then to repeat this procedure cyclically using said respective list repeatedly.

2. A digital processor according to claim 1, wherein each processing device is arranged to communicate with not more than four other processing devices, and incorporating storing means including register devices and memories connected between respective pairs of processing devices, the address set lists being such that each register device and memory is addressed by not more than one processing device at a time.

3. A digital processor according to claim 2, wherein at least some of the processing devices are arranged to communicate with two of the other processing devices via respective register devices and with a further two of the other processing devices via respective memories, and wherein the address set lists are arranged such that the register devices are addressed less frequently than the memories.

4. A digital processor according to claim 1, wherein at least some of the processing devices include input means arranged for parallel to serial conversion of input data elements.

5. A digital processor according to claim 1, wherein each processing device is arranged to store and update a respective coefficient in relation to each address set in its list.