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Method and apparatus for calibrating static timing analyzer to path delay measurements

  • US 5,845,233 A
  • Filed: 07/30/1997
  • Issued: 12/01/1998
  • Est. Priority Date: 07/30/1997
  • Status: Expired due to Term
First Claim
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1. A method of calibrating a circuit analyzer, comprising:

  • determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit;

    expressing a delay along an entire logic path of said circuit as a function of said technology parameters;

    determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and

    optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.

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