Method and apparatus for calibrating static timing analyzer to path delay measurements

• US 5,845,233 A
• Filed: 07/30/1997
• Issued: 12/01/1998
• Est. Priority Date: 07/30/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Fishburn, John Philip
• Primary Examiner(s): Barlow, Jr., John E.
• Assistant Examiner(s): VO, HIEN XUAN
• Application Number:
  US08/902,997
• Time in Patent Office: 489 Days
• Field of Search: 364/571.01, 364/488, 364/489, 364/490, 364/491, 364/578, 371/2.1, 371/2.8, 371/5.5, 371/61, 371/62, 702/57, 702/90, 702/117, 702/108
• US Class Current: 702/108
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method for calibrating a circuit analyzer includes determining a plurality of initial technology parameters characterizing the circuit according to a timing model of the circuit. A delay along an entire logic path of the circuit is expressed as a function of the technology parameters. A benchmark set of circuit paths is determined which has fixed topology, device sizes, and wire capacitances. The technology parameters are then optimized to minimize error over the set of circuit paths to obtain optimized parameters for use in the timing model. The optimized technology parameters minimize the average error for the benchmark set of paths relative to SPICE or physical measurements. Average error is significantly reduced on a representative set of paths when compared to the conventional approach of separately measuring each parameter.

Claims

1. A method of calibrating a circuit analyzer, comprising:

determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit;

expressing a delay along an entire logic path of said circuit as a function of said technology parameters;

determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and

optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.

2. A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes minimizing a sum of squares of said plurality of errors.

3. A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes varying said plurality of technology parameters within an optimization program to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.

4. A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes varying said plurality of technology parameters within an optimization program to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.

5. A method of calibrating a circuit analyzer according to claim 1, wherein said step of optimizing includes constraining said plurality of errors as conservative.

6. An apparatus for calibrating a circuit analyzer, comprising:

means for determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit;

means for expressing a delay along an entire logic path of said circuit as a function of said technology parameters;

means for determining a set of circuit paths having fixed topology, device sizes, and wire capacitances; and

a processor including means for optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.

7. An apparatus according to claim 6, wherein said means for optimizing includes means for minimizing a sum of squares of said plurality of errors.

8. An apparatus according to claim 6, wherein said means for optimizing includes means for varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.

9. An apparatus according to claim 6, wherein said means for optimizing includes means for varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.

10. An apparatus according to claim 6, wherein said means for optimizing includes means for constraining said plurality of errors as conservative.

11. A circuit analyzer for generating a graphic representation of a predicted performance of a circuit, the circuit analyzer comprising:

an input device for inputting a plurality of circuit parameters representing said circuit;

memory and stored programs for receiving and storing said circuit parameters;

a processor that is controlled by said stored programs and accesses said circuit parameters such that said processor;

expresses a delay along an entire logic path of said circuit as a function of said circuit parameters,

determines a set of circuit paths having fixed topology, device sizes, and wire capacitances,

determines said circuit parameters to predict the performance of the circuit, and

determines optimum circuit parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said processing means; and

an output device that generates a graphic representation from said processed circuit parameters.

12. An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by minimizing a sum of squares of said plurality of errors.

13. An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on actual measurement.

14. An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by varying said plurality of technology parameters to obtain a best fit of a first plurality of path delays determined using said timing model to a second plurality of path delays based on circuit simulation.

15. An apparatus according to claim 11, wherein said processor determines said optimum circuit parameters by constraining said plurality of errors as conservative.