Dimensionally stable core for use in high density chip packages

• US 5,847,327 A
• Filed: 11/08/1996
• Issued: 12/08/1998
• Est. Priority Date: 11/08/1996
• Status: Expired due to Term

• Current Assignee: Gore Enterprise Holdings Incorporated (W.L. Gore and Associates)
• Original Assignee: WL Gore and Associates Incorporated (W.L. Gore and Associates)
• Inventors: Fischer, Paul J., Sylvester, Mark F., Gorrell, Robin E.
• Primary Examiner(s): Ledynh, Bot L.
• Assistant Examiner(s): SODERQUIST, KRISTINA D
• Application Number:
  US08/747,169
• Time in Patent Office: 760 Days
• Field of Search: 174/262, 174/264, 174/265, 174/261, 174/255, 174/258, 361/792, 361/793, 361/794, 361/795, 361/719, 361/720, 361/721, 361/739, 428/308.4
• US Class Current: 174/258
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 2201/0116 Porous, e.g. foam
• CPC Class Codes: H05K 2201/015 Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 3/323 by applying an anisotropic conductive adhesive layer over an array of pads
• CPC Class Codes: H05K 3/427 initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4608 comprising an electrically conductive base or core
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/249958 Void-containing component is synthetic resin or natural rubbers
• CPC Class Codes: Y10T 442/3415 Preformed metallic film or foil or sheet [film or foil or sheet had structural integrity prior to association with the woven fabric]

Abstract

A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Claims

1. A high density chip package comprising:

a substrate having,

A) a metal core having at least one clearance formed therethrough;

B) at least one dielectric layer disposed on each of top and bottom surfaces of said metal core, said at least one dielectric layer being an expanded polytetrafluoroethylene material having an initial void volume and a mean flow pore size, said expanded polytetrafluoroethylene material having a mixture containing particulate filler and an adhesive resin, the particulate filler being a collection of individual particles having an average particle size wherein a ratio of said mean flow pore size to the average particle size is greater than about 1.4, wherein said mixture is substantially evenly distributed throughout said void volume of said expanded polytetrafluoroethylene material;

C) at least one conductive layer disposed on each of said dielectric layers; and

D) at least one conductive via electrically connecting said conductive layers;

said substrate adapted to electrically and mechanically mount a high density integrated circuit chip; and

a high density integrated circuit chip electrically and mechanically mounted on said substrate.

4. A high density chip package according to claims 1, 2 or 3, wherein said metal core is copper.

5. A high density chip package according to claims 1, 2 or 3, wherein said metal core has a thickness of approximately 1.4 mils or less.

6. A high density chip package according to claims 1, 2 or 3 wherein said at least one dielectric layer is approximately 5 microns or more thick.

7. A high density chip package according to claims 1, 2 or 3, wherein said at least one dielectric layer has a thickness in a range from about 25 microns to about 50 microns.

8. A high density chip package according to claims 1, 2 or 3, wherein said adhesive resin is cyanate ester resin.

9. The high density chip package according to claims 1, 2 or 3, wherein said metal core is a nickel alloy containing from 30 wt. % to 42 wt. % nickel with laminated copper sheets on top and bottom surfaces thereof.

2. A high density chip package comprising:

a substrate having,

A) a metal core having at least one clearance formed therethrough;

B) at least one dielectric layer disposed on each of top and bottom surfaces of said metal core, said at least one dielectric layer being an expanded polytetrafluoroethylene material having an initial void volume and a mean flow pore size, said expanded polytetrafluoroethylene material having a mixture containing particulate filler and an adhesive resin, the mixture being substantially evenly distributed throughout said void volume of said expanded polytetrafluoroethylene material, the particulate filler being a collection of individual particles, said collection containing a particle having a largest particle size which is the largest detectable particle in the collection, wherein a ratio of mean flow pore size to the largest particle size is at least about 2;

C) at least one conductive layer disposed on each of said dielectric layers; and

D) at least one conductive via electrically connecting said conductive layers;

said substrate adapted to electrically and mechanically mount a high density integrated circuit chip; and

a high density integrated circuit chip electrically and mechanically mounted on said substrate.

3. A high density chip package comprising:

a substrate having,

A) a metal core having at least one clearance formed therethrough;

B) at least one dielectric layer disposed on each of top and bottom surfaces of said metal core, said at least one dielectric layer being an expanded polytetrafluoroethylene material having an initial void volume and a minimum pore size, said expanded polytetrafluoroethylene material having a mixture containing particulate filler and an adhesive resin, the mixture being substantially evenly distributed throughout said void volume of said expanded polytetrafluoroethylene material, the particulate filler being a collection of individual particles, said collection containing a particle having a largest particle size which is the largest detectable particle in the collection, wherein a ratio of minimum pore size to the largest particle size is at least about 1.4;

C) at least one conductive layer disposed on each of said dielectric layers; and

D) at least one conductive via electrically connecting said conductive layers;

said substrate adapted to electrically and mechanically mount a high density integrated circuit chip; and

a high density integrated circuit chip electrically and mechanically mounted on said substrate.