Input protection circuit for semiconductor device

• US 5,847,430 A
• Filed: 05/29/1997
• Issued: 12/08/1998
• Est. Priority Date: 11/27/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hidaka, Hideto
• Primary Examiner(s): Whitehead, Jr., Carl W.
• Application Number:
  US08/865,264
• Time in Patent Office: 558 Days
• Field of Search: 257/173, 257/174, 257/328, 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363, 257/452, 257/546
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Between an external power supply line and an internal power supply line in which an internal power supply potential is transmitted on a substrate region, a high voltage conducting mechanism is provided, which is rendered conductive when a transitional high voltage surge is generated at the external power supply line by electrically connecting the external power supply line and the internal power supply line. Even when the ground line and external power supply line are not arranged parallel to each other, a high voltage conducting mechanism constituted by a field transistor or an insulated gate type field effect transistor having wide width over a long distance can be formed.

Claims

1. An input protection circuit for a semiconductor device, comprising:

a first power supply node on a first power supply line coupled to receive an externally applied power supply voltage at a first level;

a second power supply node on a second power supply line coupled to receive a power supply voltage corresponding to said externally applied power supply voltage and different from a ground voltage; and

a high voltage conducting mechanism having a first node coupled to said first power supply node and a second node coupled to said second power supply node, and responsive to a voltage, applied to said first power supply node, being at a second level greater than the first level, for being rendered conductive to electrically connect said first and second nodes with each other.

2. The input protection circuit according to claim 1, further comprising:

internal power supply voltage generating means for receiving the externally applied power supply voltage supplied from said first power supply node and providing an internal power supply voltage on said second power supply node.

3. The input protection circuit according to claim 1, wherein said second power supply node is coupled to receive another externally applied power supply voltage the same in potential as the power supply voltage applied to said first power supply node.

4. The input protection circuit for a semiconductor device according to claim 1, wherein

said high voltage conducting mechanism includes

a first impurity region formed at a surface of a semiconductor substrate region and connected to said first node, and

a second impurity region arranged at the surface of said semiconductor substrate region adjacent to and spaced from said first impurity region, and electrically connected to said second node.

5. The input protection circuit according to claim 4, wherein

said high voltage conducting mechanism further includes

a field insulating film formed between said first and second impurity regions, for normally isolating said first and second impurity regions.

6. The input protection circuit according to claim 4, wherein

said high voltage conducting mechanism further includes a gate electrode layer formed on said semiconductor substrate region between said first and second impurity regions with an insulating film interposed, and connected to one of said first and second nodes.

7. The input protection circuit for a semiconductor device according to claim 4, wherein

said high voltage conducting mechanism further includes

a conductive line provided between said first node and said first impurity region, for electrically connecting said first node and said first impurity region, and

an island-shaped impurity region having a common conductivity type as said first impurity region and lower impurity concentration than that of said first impurity region, formed outside and in contact with said first impurity region and at least at a region below a contact portion between said first impurity region and said conductive line.

8. The input protection circuit according to claim 4, wherein

said first and second impurity regions have a first conductivity type, and said semiconductor substrate region has a second conductivity type different from said first conductivity type.

9. The input protection circuit according to claim 4, wherein

said first impurity region has a first conductivity type, and said second impurity region and said semiconductor substrate region have a second conductivity type different from said first conductivity type.

10. The input protection circuit according to claim 3, wherein said semiconductor device includes

a data output circuit which operates using the externally applied power supply voltage applied to one of said first and second nodes as one operational power supply voltage, for outputting a received data externally.

11. The input protection circuit for a semiconductor device according to claim 3, wherein said semiconductor device comprises:

a plurality of memory cells each storing data;

a sense amplifier for sensing and amplifying data stored in a selected one of said plurality of memory cells when activated; and

sense activating means responsive to a sense activating signal for transmitting the externally applied power supply voltage applied to one of said first and second nodes to said sense amplifier.

16. The input protection circuit for a semiconductor device according to claim 1, wherein

said high voltage conducting means includes a first substrate region connected to said first node and having a circuit element using said externally applied power supply voltage formed thereon, and

a diffusion region arranged adjacent to and spaced from said substrate region in planar layout, and connected to said second node.

17. The input protection circuit according to claim 16, wherein

the circuit element formed on said first substrate region includes internal power supply voltage generating means for receiving the externally applied power supply voltage and generating an internal power supply voltage, and

said diffusion region is electrically connected to a region where an internal circuit utilizing said internal power supply voltage is formed.

18. The input protection circuit for a semiconductor device according to claim 16, wherein

said diffusion region is formed to surround said first substrate region.

19. The input protection circuit for a semiconductor device according to claim 16, wherein

said diffusion region is formed within said first substrate region.

20. The input protection circuit according to claim 1, wherein said input protection circuit and said semiconductor device are formed on a common semiconductor chip, and said second node is electrically coupled to the semiconductor chip.

21. The input protection circuit according to claim 20, wherein said second node is coupled to the semiconductor chip through a conductor line arranged along an outer periphery of the semiconductor chip and electrically connected to the chip.

12. An input protection circuit for a semiconductor device, comprising:

an external power supply pad receiving an external power supply voltage at a first level; and

a high voltage conducting means having a first node connected to said external power supply pad and a second node coupled to a semiconductor substrate region, and rendered conductive in response to a surge voltage at a second level, greater than the first level, being applied to said first node, for electrically connecting said first and second nodes with each other to absorb said surge voltage in said semiconductor substrate region,

said semiconductor substrate region is coupled to a bias source and receives a bias voltage different from a ground voltage therefrom.

13. The input protection circuit for a semiconductor device according to claim 12, wherein

said high voltage conducting means includes a first impurity region formed at a surface of said semiconductor substrate region and connected to said first node and having different conductivity type from that of said semiconductor substrate region, and

a second impurity region arranged adjacent to and apart from said first impurity region and having a common conductivity type as said semiconductor substrate region.

14. The input protection circuit for a semiconductor device according to claim 12, wherein

said high voltage conducting means includes

a plurality of junction interfaces formed by regions of different conductivity types formed between said first node and the semiconductor substrate region connected to said second node.

15. The input protection circuit according to claim 12, wherein

said high voltage conducting means includes

a first impurity region of a first conductivity type connected to said first node,

a second impurity region of the first conductivity type having lower impurity concentration than said fist impurity region, formed in contact with a lower portion of said first impurity region, and

a third impurity region of a second conductivity type formed below said first and second impurity regions on said semiconductor substrate region to surround said first and second impurity regions.