Solid-state image sensing device

• US 5,847,594 A
• Filed: 04/25/1997
• Issued: 12/08/1998
• Est. Priority Date: 04/26/1996
• Status: Expired due to Term

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: Mizuno, Seiichiro
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/845,427
• Time in Patent Office: 592 Days
• Field of Search: 327/514, 327/515, 327/337, 327/344, 327/345
• US Class Current: 327/514
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/57 Control of the dynamic range

Abstract

When a photodiode receives light, it produces a charge corresponding to the intensity of light, and outputs it as a current signal. The current signal is input to an integral circuit constituted by a feedback capacitive element and a charge amplifier, and is integrated by time. On the other hand, a step charge generator generates a charge corresponding to one of reference voltage levels +Vref and -Vref in response to first and second clock signals CLK1 and CLK2, and supplies the charge to the feedback capacitive element in synchronism with the clock signal. The integral circuit executes an integral operation by accumulating the charge produced by the photodiode, and supplies a step charge, thus executing ΣΔ modulation. An AD conversion result is obtained from the ΣΔ modulation result. In this manner, high-precision digital data is output in correspondence with the intensity of light by the photodiode with a simple circuit arrangement.

Claims

1. A solid-state image sensing device comprising:

a photodiode for producing a charge in correspondence with an intensity of light thereby, said photodiode having a first terminal set at a first reference voltage level and a second terminal for outputting the produced charge, and the first reference voltage level falling within a range between second and third reference voltage levels;

a first feedback capacitive element having a first terminal which directly receives the charge output from the second terminal of said photodiode;

a first amplifier having a signal input terminal connected to the first terminal of said first feedback capacitive element, the signal input terminal of said first amplifier being virtually set at the first reference voltage level, and an output terminal of said first amplifier being connected to a second terminal of said first feedback capacitive element;

a first step charge generator for producing a step charge on the basis of the second and third reference voltage levels, the first step charge generator supplying the step charge to said first feedback capacitive element;

a voltage comparator for receiving a first integral voltage signal output from said first amplifier, comparing a voltage of the first integral voltage signal with the first reference voltage level, and outputting a comparison result signal;

a binary sampling circuit for receiving the comparison result signal, and sampling the comparison result signal to binarize the comparison result signal; and

a fundamental timing generation circuit for generating a first clock signal and a second clock signal being at logical false level when the first clock signal is at logical truth level and changing to logical truth level during a period included in a logical false level period of the first clock signal, outputting the first and second clock signals to said first step charge generator, and outputting the first clock signal to said binary sampling circuit.

2. A device according to claim 1, further comprising:

a first step charge generation control circuit for receiving an output signal from said binary sampling circuit, and outputting the output signal from said binary sampling circuit and an inverted signal of the output signal from said binary sampling circuit to said first step charge generator as a step charge generation instruction.

3. A device according to claim 2, wherein said first step charge generator comprises:

a first switch having a first terminal set at the second reference voltage level and being opened/closed in response to the output signal from said binary sampling circuit;

a second switch having a first terminal set at the third reference voltage level and being opened/closed in response to the inverted signal of the output signal from said binary sampling circuit;

a third switch having a first terminal set at the first reference voltage level and being opened/closed in response to the first clock signal;

a fourth switch having a first terminal set at the first reference voltage level and being opened/closed in response to the first clock signal;

a first step charge generation capacitive element having a first terminal connected to a second terminal of said third switch and a second terminal connected to a second terminal of said fourth switch;

a fifth switch having a first terminal connected to the first terminal of said first step charge generation capacitive element and a second terminal connected to the signal input terminal of said first amplifier, and being opened/closed in response to the second clock signal; and

a sixth switch having a first terminal connected to second terminals of said first and second switches and a second terminal connected to the second terminal of said first step charge generation capacitive element, and being opened/closed in response to the second clock signal.

4. A device according to claim 1, further comprising:

a dark current removing circuit for removing a dark current of said photodiode.

5. A device according to claim 4, wherein said dark current removing circuit comprises:

a field effect transistor having a source terminal connected to the signal input terminal of said first amplifier and a drain terminal set at the first reference voltage level;

a dark current storage capacitive element having a first terminal connected to a gate terminal of said field effect transistor and a second terminal set at the first reference voltage level; and

a current holding switch having a first terminal connected to the first terminal of said dark current storage capacitive element and a second terminal connected to the output terminal of said first amplifier.

6. A device according to claim 1, further comprising, between said first amplifier and said voltage comparator:

a signal sampling circuit for sampling the first integral voltage signal at an instructed timing, and outputting an AC component signal;

a feedback capacitance circuit having a second feedback capacitive element for receiving a signal output from said signal sampling circuit at a first terminal thereof;

a second amplifier for receiving the signal output from said signal sampling circuit at a signal input terminal thereof, an output terminal of said second amplifier being connected to said feedback capacitance circuit; and

a second step charge generator for generating a step charge on the basis of the second and third reference voltage levels and supplying the step charge to said second feedback capacitive element, and wherein said voltage comparator receives a second integral voltage signal output from said second amplifier.

7. A device according to claim 6, further comprising:

a second step charge generation control circuit for receiving an output signal from said binary sampling circuit, and outputting the output signal from said binary sampling circuit and an inverted signal of the output signal from said binary sampling circuit to said first and second step charge generators as a step charge generation instruction.

8. A device according to claim 7, wherein said signal sampling circuit comprises:

a first switch having a first terminal connected to the output terminal of said first amplifier and being opened/closed in response to the first clock signal; and

a signal transmission capacitive element having a first terminal connected to a second terminal of said first switch and a second terminal connected to the signal input terminal of said second amplifier.

9. A device according to claim 8, wherein said second step charge generator comprises:

a second switch having a first terminal set at the second reference voltage level and being opened/closed in response to the output signal from said binary sampling circuit;

a third switch having a first terminal set at the third reference voltage level, and being opened/closed in response to the inverted signal of the output signal from said binary sampling circuit; and

a fourth switch having a first terminal connected to second terminals of said second and third switches and a second terminal connected to the first terminal of said signal transmission capacitive element, and being opened/closed in response to the second clock signal, and

said feedback capacitance circuit comprises;

said second feedback capacitive element having the first terminal connected to the signal input terminal of said second amplifier;

a fifth switch having a first terminal connected to a second terminal of said second feedback capacitive element and a second terminal connected to the output terminal of said second amplifier, and being opened/closed in response to the first clock signal; and

a sixth switch having a first terminal connected to the signal input terminal of said second amplifier and a second terminal connected to the output terminal of said second amplifier, and being opened/closed in response to the first clock signal.

10. A device according to claim 7, wherein said signal sampling circuit comprises:

a first switch having a first terminal connected to the output terminal of said first amplifier and being opened/closed in response to the first clock signal;

a signal transmission capacitive element having a first terminal connected to a second terminal of said first switch;

a second switch having a first terminal connected to a second terminal of said signal transmission capacitive element and a second terminal connected to the signal input terminal of said second amplifier, and being opened/closed in response to the second clock signal;

a third switch having a first terminal set at the first reference voltage level and a second terminal connected to the first terminal of said signal transmission capacitive element, and being opened/closed in response to the second clock signal; and

a fourth switch having a first terminal set at the first reference voltage level and a second terminal connected to the second terminal of said signal transmission capacitive element, and being opened/closed in response to the first clock signal.

11. A device according to claim 10, wherein said second step charge generator comprises:

a fifth switch having a first terminal set at the second reference voltage level, and being opened/closed in response to the output signal from said binary sampling circuit;

a sixth switch having a first terminal set at the third reference voltage level, and being opened/closed in response to the inverted signal of the output signal from said binary sampling circuit;

a seventh switch having a first terminal set at the first reference voltage level, and being opened/closed in response to the first clock signal;

an eighth switch having a first terminal set at the first reference voltage level, and being opened/closed in response to the first clock signal;

a second step charge generation capacitive element having a first terminal connected to a second terminal of said seventh switch and a second terminal connected to a second terminal of said eighth switch;

a ninth switch having a first terminal connected to the first terminal of said second step charge generation capacitive element and a second terminal connected to the signal input terminal of said second amplifier, and being opened/closed in response to the second clock signal; and

a tenth switch having a first terminal connected to second terminals of said fifth and sixth switches and a second terminal connected to the second terminal of said second step charge generation capacitive element, and being opened/closed in response to the second clock signal, and

said feedback capacitance circuit comprises said second feedback capacitive element having the first terminal connected to the signal input terminal of said second amplifier and a second terminal connected to the output terminal of said second amplifier.

12. A device according to claim 1, further comprising:

a digital filter circuit for receiving a digital signal sequence output from said binary sampling circuit, and outputting a digitally filtered data signal.

13. A device according to claim 1, wherein capacitances of said first feedback capacitive element and said first step charge generator are selected in correspondence with time characteristics of an output current from said photodiode.

14. A device according to claim 1, wherein a plurality of photodiodes being equivalent to said photodiode, and the plurality of photodiodes being arranged in one of one- and two-dimensional arrays, and said device further comprises a selection circuit for selecting one of said photodiodes to be connected to the first terminal of said first feedback capacitive element.

15. A device according to claim 14, wherein said selection circuit selects said photodiodes in one of a predetermined order and a random order.