Variable-path-length voltage-controlled oscillator circuit

• US 5,847,617 A
• Filed: 08/11/1997
• Issued: 12/08/1998
• Est. Priority Date: 08/12/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Cliff, Richard G., Reddy, Srinivas T., McClintock, Cameron, Jefferson, David Edward
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/909,337
• Time in Patent Office: 484 Days
• Field of Search: 331/1 A, 331/8, 331/17, 331/25, 331/34, 331/57, 331/177 RV, 331/179, 327/105-107, 327/156-159
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.

Claims

1. A programmable logic device that is proarammed using a programmable logic device programmer comprising:

a series of linked inverter stages having controllable delay times;

a path length selection circuit that forms a ring oscillator having a selected path length from the inverter stages in response to path length configuration data;

an oscillator output connected to the ring oscillator that provides an output signal with a frequency determined by the selected path length and by the delay times of the inverter stages; and

programmable memory that is configured to store the path length configuration data and that is programmed with the path length configuration data using the programmable logic device programmer.

2. The programmable logic device defined in claim 1 wherein the path length selection circuit comprises a multiplexer having a path output connected to one end of the series of linked inverter stages and having a plurality of path inputs each connected to a point in the series of linked inverter stages between a different pair of adjacent inverter stages, the selected path length being formed by connecting a selected one of the path inputs to the path output in response to the path length configuration data.

3. The programmable logic device defined in claim 1 wherein the inverter stages are controlled by a common voltage-control signal received in parallel by all of the inverter stages, the oscillator circuit further comprising:

a phase detector that receives a reference signal and a compare signal and generates a corresponding error signal; and

a low-pass filter that filters the error signal and provides the filtered error signal to the inverter stages as the common voltage-control signal.

4. The programmable logic device defined in claim 3 further comprising a divide-by-N circuit for dividing the frequency of the signal at the oscillator output by N and passing the resulting signal to the phase detector as the compare signal.

5. The programmable logic device defined in claim 1 wherein the path length selection circuit comprises a multiplexer having a path output connected to one end of the series of linked inverter stages and having a plurality of path inputs each connected to a point in the series of linked inverter stages between a different pair of adjacent inverter stages, the selected path length being formed by connecting a selected one of the path inputs to the path output.

6. The programmable logic device defined in claim 1 wherein the inverter stages are current-starved inverter stages.

7. The programmable logic device defined in claim 1 wherein the inverter stages are variable-capacitive-load inverter stages.

8. The programmable logic device defined in claim 1 wherein the inverter stages are differential-delay inverter stages.

9. The programmable logic device defined in claim 1 further comprising a phase detector that provides an error signal to the inverter stages in the form of a voltage control signal that controls the delays of the inverter stages.

10. The programmable logic device defined in claim 1 wherein the programmable memory is a random-access memory.

11. A programmable logic device that is programmed using a programmable logic device programmer comprising:

a series of linked inverter stages each having an input for a control voltage and each having a delay time controlled by the magnitude of the control voltage;

a path length selection circuit connected to the linked inverter stages to form a ring oscillator having a selected one of various path lengths in response to path length configuration data;

a ring oscillator output that provides an output signal at a frequency determined by the selected path length and the magnitude of the control voltage; and

programmable memory that is configured to store the path length configuration data and that is programmed with the path length configuration data using the programmable logic device programmer.

12. The programmable logic device defined in claim 11 further comprising:

a phase detector for generating an error signal based on the comparison of a reference signal and a compare signal;

a filter for filtering the error signal and providing the filtered error signal to the inverter stages as the control voltage; and

a divide-by-N circuit for dividing the frequency of the ring oscillator output signal and passing the resulting signal to the phase detector as the compare signal.