Ram cell capable of storing 3 logic states
First Claim
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1. A memory cell which comprises:
- an impedance transistor having a first terminal, a second terminal, and a gate, said gate is configured to store a charge indicative of a data magnitude;
a flip-flop having an input node, and an output node, wherein said output node is coupled to said first terminal of said impedance transistor, said flip-flop is configured to hold a state indicative of a data sign;
a read transistor coupled to said second terminal of said impedance transistor, said read transistor configured to conduct a current through said impedance transistor when a read signal is asserted;
a first write transistor coupled to said input node, said first write transistor configured to set the state of said flip-flop when a write signal is asserted; and
a second write transistor coupled to said gate of said impedance transistor, said second write transistor configured to store said charge on said gate when said write signal is asserted.
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Abstract
A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.
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5 Claims
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1. A memory cell which comprises:
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an impedance transistor having a first terminal, a second terminal, and a gate, said gate is configured to store a charge indicative of a data magnitude; a flip-flop having an input node, and an output node, wherein said output node is coupled to said first terminal of said impedance transistor, said flip-flop is configured to hold a state indicative of a data sign; a read transistor coupled to said second terminal of said impedance transistor, said read transistor configured to conduct a current through said impedance transistor when a read signal is asserted; a first write transistor coupled to said input node, said first write transistor configured to set the state of said flip-flop when a write signal is asserted; and a second write transistor coupled to said gate of said impedance transistor, said second write transistor configured to store said charge on said gate when said write signal is asserted. - View Dependent Claims (2, 3, 4, 5)
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Specification