Method and apparatus for stress testing a semiconductor memory
First Claim
1. An apparatus for stress testing a semiconductor memory having a sense amplifier coupled to one of a plurality of pairs of complementary bitlines within a memory sub-array of the semiconductor memory through a pair of isolation switches, the apparatus comprising:
- another pair of isolation switches for switchably coupling the sense amplifier to another one of the pairs of complementary bitlines in the memory sub-array; and
circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the semiconductor memory.
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Accused Products
Abstract
Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.
21 Citations
20 Claims
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1. An apparatus for stress testing a semiconductor memory having a sense amplifier coupled to one of a plurality of pairs of complementary bitlines within a memory sub-array of the semiconductor memory through a pair of isolation switches, the apparatus comprising:
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another pair of isolation switches for switchably coupling the sense amplifier to another one of the pairs of complementary bitlines in the memory sub-array; and circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the semiconductor memory. - View Dependent Claims (2, 3)
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4. A semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bitlines coupled to the memory sub-array; a sense amplifier; a pair of isolation switches coupled between the sense amplifier and one of the pairs of complementary bitlines; another pair of isolation switches coupled between the sense amplifier and another one of the pairs of complementary bitlines; and circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the semiconductor memory. - View Dependent Claims (5, 6, 7, 8)
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9. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bitlines coupled to the memory sub-array; a sense amplifier; a pair of isolation switches coupled between the sense amplifier and one of the pairs of complementary bitlines; another pair of isolation switches coupled between the sense amplifier and another one of the pairs of complementary bitlines; and circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the semiconductor memory. - View Dependent Claims (10, 11, 12, 13)
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14. A semiconductor wafer on which is fabricated a semiconductor memory comprising:
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a memory sub-array; a plurality of pairs of complementary bitlines coupled to the memory sub-array; a sense amplifier; a pair of isolation switches coupled between the sense amplifier and one of the pairs of complementary bitlines; another pair of isolation switches coupled between the sense amplifier and another one of the pairs of complementary bitlines; and circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the semiconductor memory. - View Dependent Claims (19)
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15. A Dynamic Random Access Memory (DRAM) device comprising:
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a DRAM sub-array; a plurality of pairs of complementary bitlines coupled to the DRAM sub-array; a plurality of sense amplifiers; a pair of isolation switches coupled between one of the sense amplifiers and one of the pairs of complementary bitlines; another pair of isolation switches coupled between the one of the sense amplifiers and another one of the pairs of complementary bitlines; and circuitry coupled to both pairs of isolation switches for activating the switches at substantially the same time during a stress test of the DRAM device. - View Dependent Claims (16, 20)
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- 17. A method of stress testing a semiconductor memory, the method comprising switchably coupling a sense amplifier of the semiconductor memory to at least two pairs of complementary bitlines in the same memory sub-array of the semiconductor memory at substantially the same time during a stress test of the semiconductor memory.
Specification