ATM communication system interconnect/termination unit
First Claim
1. An asynchronous transfer mode (ATM) communication device for use in an ATM communication system network, said device comprising:
- memory means for receiving, storing and recovering ATM conversion sublayer protocol data units (CS-PDU'"'"'s);
a scheduler processor permanently pre-configured to maintain a calendar-based scheduler table having entries of virtual circuits (VC'"'"'s) to be serviced in sequential cell slot time intervals to receive CS-PDU'"'"'s from said memory means;
a pre-configured timer having means for maintaining plural hardware-implemented timers accessible to said scheduler processor to measure said cell slot time intervals and schedule VC services therein.
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Abstract
An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU'"'"'s) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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Citations
18 Claims
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1. An asynchronous transfer mode (ATM) communication device for use in an ATM communication system network, said device comprising:
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memory means for receiving, storing and recovering ATM conversion sublayer protocol data units (CS-PDU'"'"'s); a scheduler processor permanently pre-configured to maintain a calendar-based scheduler table having entries of virtual circuits (VC'"'"'s) to be serviced in sequential cell slot time intervals to receive CS-PDU'"'"'s from said memory means; a pre-configured timer having means for maintaining plural hardware-implemented timers accessible to said scheduler processor to measure said cell slot time intervals and schedule VC services therein. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data-structure driven asynchronous transfer mode (ATM) communication device for receiving, processing, and transmitting a plurality of data cells in an ATM communication system network, said device comprising:
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memory means for receiving, storing and recovering ATM conversion sublayer protocol data units (CS-PDU'"'"'s ); and
data-structures of linked lists with memory address pointers to starting and ending memory addresses as well as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression;a scheduler processor permanently pre-configured to maintain a calendar-based scheduler table having entries of virtual circuits (VC'"'"'s ) to be serviced in sequential cell slot time intervals to receive CS-PDU'"'"'s from said memory means; a pre-configured timer having means for maintaining plural hardware-implemented timers accessible to said scheduler processor to measure said cell slot time intervals and schedule VC services therein; a programmable processor exercising executive control over said scheduler processor and said pre-configured timer, said programmable processor creating in said memory means a descriptor for each of said data-structures of linked lists; and a processor memory accessible to said programmable processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification