Apparatus and process for sampling a serial digital signal

• US 5,848,109 A
• Filed: 08/02/1995
• Issued: 12/08/1998
• Est. Priority Date: 08/04/1994
• Status: Expired due to Term

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Cofler, Andrew, Couteaux, Pascal, Le Bihan, Jean-Claude, Nezamzadeh-Moosavi, Reza, Duplessix, Anne Pierre, Marbot, Roland
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Corrielus, Jean B.
• Application Number:
  US08/510,458
• Time in Patent Office: 1,224 Days
• Field of Search: 375/355, 375/373, 375/376, 341/54, 341/70, 341/100, 341/112, 327/141, 327/161, 327/162, 327/163
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

Claims

1. A process for sampling a serial digital signal (D) representative of recurring bits and having transitions, comprising the steps of phasing the digital signal with a clock signal (C) and sampling the digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of the digital signal, said phasing step including determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal and comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling step including controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation.

2. The process according to claim 1, wherein said step of comparing said phasing test instants with the respective transition occurrences in the digital signal includes getting phasing samples (DPi) at said phasing test instants and detecting said transition occurrences.

3. The process according to claim 2, wherein each of said transitions of the serial digital signal has a direction and said comparing step further includes determining the direction of said detected transitions.

4. The process according to claim 1, wherein said controlling step is performed after a predetermined number of said comparing steps.

5. The process according to claim 4, wherein said clock signal has recurring periods (T) and the predetermined number of said comparing steps corresponds to a predetermined number of said consecutive recurring periods of the clock signal.

6. The process according to claim 1, wherein said sampling instants are delayed from said clock signal by a delay Xi=kR/2+iR, where k is a positive whole odd number other than 0, i is 0 and/or a positive whole number and R designates a period of said recurring bits in said digital signal.

7. The process according to claim 6, wherein said phasing test instants are delayed from said sampling instants by a complementary delay Y=k'"'"'R/2, wherein k'"'"' is a positive whole odd number other than 0.

8. The process according to claim 7, further including performing a phasing test by detecting a transition of said digital signal and verifying whether a value of the digital signal at one of said phasing test instants corresponds to a phase lead or a phase lag relative to said transition.

9. The process of claim 6, wherein said clock signal has transitions and a period (T) which corresponds to a maximal number representative of said number i of recurring bits in said digital signal, and said sampling instants are delayed from predetermined transitions of said clock signal.

10. The process according to claim 1, wherein said phasing step further includes controlling the phasing test instants in accordance with said phase deviation.

11. A process for sampling a serial digital signal (D) representative of recurring bits and having transitions, comprising the steps of phasing the digital signal with a clock signal (C) and sampling the digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of the digital signal, said phasing step including determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal and comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling step including controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation and further comprising assigning limit values to delays (Xi) of the delayed sampling instants and, when said limit values are reached, shifting said delayed sampling instants (Si) by one pulse repetition period R of bits of said digital signal, and compensating for said shifting so as to reconstruct all said bits of said digital signal.

12. A transmission system (1) comprising an emitter (2) for transmitting a serial digital signal (D) representative of bits recurring at a period (R) and having transitions and a receiver (4) for receiving said serial digital signal, said receiver having an internal clock (5) which generates a clock signal (C), means (10) for phasing said digital signal with said clock signal, and means (20) for sampling said digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of said digital signal, said phasing means including means for determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal and means connected to said determining means for comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling means including means connected to said phase comparison means for controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation.

13. The transmission system according to claim 12, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, a second group of controllable delay elements (24) which are controlled to have respective outputs representative of the sampling instants (Si) and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi), the delay elements of the first, second and third groups being serially connected, respectively.

14. The transmission system according to claim 13, wherein said phasing test instants are controlled in accordance with said phase deviation.

15. The transmission system according to claim 12, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, an additional controllable delay element (24) which is controlled to have a delay (X) representative of the shorter of the sampling instants, which additional delay element receives the clock signal and is serially connected to a second group of cascaded controllable delay elements (22'"'"') which are controlled by said digital control signal to have a delay representative of said recurring period of said bits of said digital signal and to have respective outputs representative of the sampling instants (Si), and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi) and are connected to respective outputs of the additional delay element and the delay elements of said second group.

16. The transmission system according to claim 15, wherein said phasing test instants are controlled in accordance with said phase deviation.

17. The transmission system according to claim 12, wherein said means for sampling includes means for determining limit values for a delay of said delayed sampling instants, means for shifting the delayed sampling instants when the delay of the delayed sampling instants reaches one of said limit values, and means for compensating for the shifting of the delayed sampling instants in order to reconstruct all bits of the digital signal.

18. The transmission system according to claim 12, wherein said phasing means further includes means (30) for controlling said phasing test instants in accordance with said phase deviation.

19. An integrated circuit comprising a receiver of a serial digital signal (D) representative of bits recurring at a period (R) and having transitions, said receiver having an internal clock (5) which generates a clock signal (C), means (10) for phasing said digital signal with said clock signal and means (20) for sampling said digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of said digital signal, said phasing means including means for determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal, and said sampling means including means connected to said determining means for comparing said phasing test instants with respective transition occurrences in the digital signal and determining a phase deviation therebetween and means connected to said phase comparison means for controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation.

20. The integrated circuit according to claim 19, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, a second group of controllable delay elements (24) which are controlled to have respective outputs representative of the sampling instants (Si) and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi), the delay elements of the first, second and third groups being serially connected, respectively.

21. The integrated circuit according to claim 19, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, an additional controllable delay element (24) which is controlled to have a delay (X) representative of the shorter of the sampling instants, which additional delay element receives the clock signal and is serially connected to a second group of cascaded controllable delay elements (22'"'"') which are controlled by said digital control signal to have a delay representative of said recurring period of said bits of said digital signal and to have respective outputs representative of the sampling instants (Si), and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi) and are connected to respective outputs of the additional delay element and the delay elements of said second group.

22. The integrated circuit according to claim 21, wherein said phasing test instants are controlled in accordance with said phase deviation.

23. The integrated circuit according to claim 19, wherein said means for sampling includes means for determining limit values for a delay of said delayed sampling instants, means for shifting the delayed sampling instants when the delay of the delayed sampling instants reaches one of said limit values, and means for compensating for the shifting of the delayed sampling instants in order to reconstruct all bits of the digital signal.

24. The integrated circuit according to claim 23, wherein said phasing test instants are controlled in accordance with said phase deviation.

25. The integrated circuit according to claim 19, wherein said phasing means further includes means (30) for controlling said phasing test instants in accordance with said phase deviation.

26. A process for sampling a serial digital signal (D) representative of recurring bits and having transitions, comprising the steps of phasing the digital signal with a clock signal (C) and sampling the digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of the digital signal, said phasing step including determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal and comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling step including controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation and wherein said phasing test instants are delayed from said sampling instants by a complementary delay Y=k'"'"'R/2, wherein k'"'"' is a positive whole odd number other than 0 and R is said period of the recurring bits in said digital signal (D).

27. A process for sampling a serial digital signal (D) representative of recurring bits and having transitions, comprising the steps of phasing the digital signal with a clock signal (C) and sampling the digital signal at sampling instants (Si) delayed from said clock signal to have samples (DSi) representative of bits of the digital signal, said phasing step including determining phasing test instants (Pi) delayed from said sampling instants to substantially occur at respective possible transitions of the digital signal and comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling step including controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation and wherein said step of determining said phasing test instants includes generating a reference signal referring to said sampling instants and said comparing step includes comparing said reference signal with said digital signal.

28. A process for sampling a serial digital signal (D) representative of bits recurring at a period (R), comprising the steps of phasing the digital signal with a clock signal (C) having a period (T) which corresponds to a number of periods of the recurring bits in the digital signal, and sampling the digital signal at sampling instants (Si) to have samples (DSi) representative of the bits of the digital signal, said sampling instants being delayed from said clock signal by a delay Xi=kR/2+iR, where k is a positive whole odd number other than 0 and i is 0 and/or a positive whole number having a maximal value corresponding to said number of bit periods in said clock period less one, said phasing step including determining phasing test instants (Pi) to substantially occur at respective possible transitions of the digital signal, said phasing test instants being delayed from said sampling instants by a complementary delay Y=k'"'"'R/2, where k'"'"' is a positive whole odd number other than 0, and comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling step including controlling said sampling instants to be delayed in accordance with said phase deviation.

29. The process according to claim 28, wherein said phasing step further includes controlling the phasing test instants in accordance with said phase deviation.

30. The process according to claim 28, further comprising assigning limit values to delays (Xi) of the delayed sampling instants and, when said limit values are reached, shifting said delayed sampling instants and, when said limit values are reached, shifting said delayed sampling instants (Si) by one pulse repetition period R of bits of said digital signal, and compensating for said shifting so as to reconstruct all said bits of said digital signal.

31. A transmission system (1) comprising an emitter (2) for transmitting a serial digital signal (D) representative of bits recurring at a period (R) and having transitions and a receiver (4) for receiving said serial digital signal, said receiver having an internal clock signal (C) having a period (T) which corresponds to a number of periods of the recurring bits in the digital signal, means (10) for phasing said digital signal with said clock signal and means (20) for sampling said digital signal at sampling instants (Si) to have samples (DSi) representative of the bits of the digital signal, said sampling instants being delayed from said clock signal by a delay Xi=kR/2+iR, where k is a positive whole odd number other than 0 and i is 0 and/or a positive whole number having a maximal value corresponding to said number of bit periods in said clock period less one, said phasing step including means for determining phasing test instants (Pi) to substantially occur at respective possible transitions of the digital signal, said phasing test instants being delayed from said sampling instants by a complementary delay Y=k'"'"'R/2, where k'"'"' is a positive whole odd number other than 0, and means connected to said determining means for comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling means including means connected to said phase comparison means for controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation.

32. The transmission system according to claim 31, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, a second group of controllable delay elements (24) which are controlled to have respective outputs representative of the sampling instants (Si) and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi), the delay elements of the first, second and third groups being serially connected, respectively.

33. The transmission system according to claim 31, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, an additional controllable delay element (24) which is controlled to have a delay (X) representative of the shorter of the sampling instants, which additional delay element receives the clock signal and is serially connected to a second group of cascaded controllable delay elements (22'"'"') which are controlled by said digital control signal to have a delay representative of said recurring period of said bits of said digital signal and to have respective outputs representative of the sampling instants (Si), and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi) and are connected to respective outputs of the additional delay element and the delay elements of said second group.

34. The transmission system according to claim 33, wherein said phasing test instants are controlled in accordance with said phase deviation.

35. The transmission system according to claim 31, wherein said means for sampling includes means for determining limit values for a delay of said delayed sampling instants, means for shifting the delayed sampling instants when the delay of the delayed sampling instants reaches one of said limit values, and means for compensating for the shifting of the delayed sampling instants in order to reconstruct all bits of the digital signal.

36. The transmission system according to claim 35, wherein said phasing test instants are controlled in accordance with said phase deviation.

37. The transmission system according to claim 31, wherein said phasing means further includes means (30) for controlling said phasing test instants in accordance with said phase deviation.

38. An integrated circuit comprising a receiver (4) for receiving a serial digital signal (D) representative of bits recurring at a period (R) and having transitions, said receiver having an internal clock signal (C) having a period (T) which corresponds to a number of periods of the recurring bits in the digital signal, means (10) for phasing said digital signal with said clock signal and means (20) for sampling said digital signal at sampling instants (Si) to have samples (DSi) representative of the bits of the digital signal, said sampling instants being delayed from said clock signal by a delay Xi=kR/2+iR, where k is a positive whole odd number other than 0 and i is 0 and/or a positive whole number having a maximal value corresponding to said number of bit periods in said clock period less one, said phasing step including means for determining phasing test instants (Pi) to substantially occur at respective possible transitions of the digital signal, said phasing test instants being delayed from said sampling instants by a complementary delay Y=k'"'"'R/2, where k'"'"' is a positive whole odd number other than 0, and means connected to said determining means for comparing said phasing test instants with respective transition occurrences in the digital signal to determine a phase deviation therebetween, and said sampling means including means connected to said phase comparison means for controlling said sampling instants to be delayed from said clock signal in accordance with said phase deviation.

39. The integrated circuit according to claim 38, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, a second group of controllable delay elements (24) which are controlled to have respective outputs representative of the sampling instants (Si) and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi), the delay elements of the first, second and third groups being serially connected, respectively.

40. The integrated circuit according to claim 38, wherein said means for phasing and sampling includes a phase locked loop circuit having a phase comparator (21) with first and second inputs and an output, said first input (21a) receiving the clock signal directly and said second output supplying a phasing signal, digital control means (23) connected to said output of said comparator for generating a digital control signal (CTL), a first group of cascaded controllable delay elements (22), which first group of controllable delay elements has an input for receiving the clock signal and an output connected to said second input (21b) of said phase comparator, each of said controllable delay elements being controlled by said digital control signal to have a delay representative of said recurring period (R) of bits of said digital signal, an additional controllable delay element (24) which is controlled to have a delay (X) representative of the shorter of the sampling instants, which additional delay element receives the clock signal and is serially connected to a second group of cascaded controllable delay elements (22'"'"') which are controlled by said digital control signal to have a delay representative of said recurring period of said bits of said digital signal and to have respective outputs representative of the sampling instants (Si), and a third group of controllable delay elements (26) which are controlled to have respective outputs representative of the phasing instants (Pi) and are connected to respective outputs of the additional delay element and the delay elements of said second group.

41. The integrated circuit according to claim 40, wherein said phasing test instants are controlled in accordance with said phase deviation.

42. The integrated circuit according to claim 38, wherein said means for sampling includes means for determining limit values for a delay of said delayed sampling instants, means for shifting the delayed sampling instants when the delay of the delayed sampling instants reaches one of said limit values, and means for compensating for the shifting of the delayed sampling instants in order to reconstruct all bits of the digital signal.

43. The integrated circuit according to claim 42, wherein said phasing test instants are controlled in accordance with said phase deviation.

44. The integrated circuit according to claim 38, wherein said phasing means further includes means (30) for controlling said phasing test instants in accordance with said phase deviation.