Serial interrrupt control system in a system in which a plurality of interrupt requesters are connected to a serial bus

• US 5,848,278 A
• Filed: 09/25/1996
• Issued: 12/08/1998
• Est. Priority Date: 09/29/1995
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakai, Makoto
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Kim, Harold J.
• Application Number:
  US08/719,215
• Time in Patent Office: 804 Days
• Field of Search: 395/740, 395/739, 395/868, 395/734, 395/185.03, 395/555, 395/859, 395/551, 395/559, 395/733-742
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

In an interrupt control system to be applied, especially, to a laptop or notebook type personal computer that can use an expansion unit, an interrupt encoder converts the leading edges of a plurality of interrupt signals into serial data and transfers the serial data to an interrupt decoder. The interrupt decoder converts the serial data into original parallel interrupt signals, and outputs these signals to a programmable interrupt controller. A bridge circuit generates an idle cycle of a secondary bus by detecting the idle cycle of a primary bus, and generates latch pulses for interrupt serial data of the secondary bus.

Claims

1. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting level transitions of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data, the interrupt encoder means comprising means for converting the parallel interrupt signals into the serial data by detecting leading edges of the parallel interrupt signals; and

means for detecting leading edges of the interrupt signals in synchronism with interrupt decoder means by detecting an idle cycle;

serial transfer means for transferring the serial data; and

interrupt decoder means for converting the serial data transferred by said serial transfer means into the parallel interrupt signals, and supplying the parallel interrupt signals to said interrupt controller, the interrupt decoder means comprising means for generating the idle cycle.

2. A system according to claim 1, wherein said interrupt decoder means comprises:

means for generating an idle cycle;

and said interrupt encoder means comprises;

means for generating latch pulses used for said interrupt encoder means to detect the leading edges of the interrupt signals by detecting the idle cycle; and

means for detecting the leading edges of the interrupt signals in response to the latch pulses.

3. A system according to claim 1, wherein the idle cycle consists of a cycle for attaining synchronization, and cycles corresponding in number to the interrupt signals, the cycle for attaining synchronization is driven to active level by said interrupt decoder means, and the remaining cycles are driven by said interrupt decoder means to non-active level.

4. A system according to claim 3, wherein said interrupt encoder means comprises means for converting the interrupt signals into serial data by driving to active level the cycles corresponding to the interrupt signals whose leading edges are detected.

5. A system according to claim 1, wherein said interrupt decoder means comprises means which are arranged in correspondence with the number of the interrupt signals, and independently detect the leading edges in units of interrupt signals.

6. A system according to claim 1, wherein said interrupt decoder means comprises:

means for generating an internal interrupt request signal to said interrupt controller on the basis of leading edge information supplied from said interrupt encoder means; and

means for canceling the internal interrupt request signal in synchronism with a timing at which said interrupt controller latches the internal interrupt request signal.

7. A system according to claim 1, wherein said serial transfer means comprises a clock signal line and a serial data line.

8. A system according to claim 1, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

9. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting leading edges and trailing edges of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data, the interrupt encoder means comprising means for detecting the leading edges and the trailing edges of the interrupt signals in synchronism with interrupt decoder means by detecting an idle cycle;

serial transfer means for transferring the serial data; and

interrupt decoder means for converting the serial data transferred by said serial transfer means into the parallel interrupt signals, and supplying the parallel interrupt signals to said interrupt controller, the interrupt decoder means comprising means for generating the idle cycle.

10. A system according to claim 9, wherein said interrupt decoder means comprises means for generating an idle cycle;

and said interrupt encoder means comprises;

means for generating latch pulses used for said interrupt encoder means to detect the leading edges of the interrupt signals by detecting the idle cycle; and

means for detecting the leading edges and the trailing edges of the interrupt signals in response to the latch pulses.

11. A system according to claim 9, wherein the idle cycle consists of a cycle for attaining synchronization, and cycles corresponding in number to the interrupt signals, the cycle for attaining synchronization is driven to active level by said interrupt decoder means, and the remaining cycles are driven by said interrupt decoder means to non-active level.

12. A system according to claim 9, wherein said interrupt encoder means comprises means for converting the interrupt signals into serial data by driving to active level the cycles corresponding to the interrupt signals whose leading edges and trailing edges are detected.

13. A system according to claim 9, wherein said interrupt decoder means comprises means which are arranged in correspondence with the number of the interrupt signals, and independently detect the leading edges and the trailing edges in units of interrupt signals.

14. A system according to claim 9, wherein said interrupt decoder means comprises:

means for generating an internal interrupt request signal to said interrupt controller on the basis of leading edge information and trailing edge information supplied from said interrupt encoder means; and

means for canceling the internal interrupt request signal in synchronism with a timing at which said interrupt controller latches the internal interrupt request signal.

15. A system according to claim 9, wherein said serial transfer means comprises a clock signal line and a serial data line.

16. A system according to claim 9, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

17. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting at least one of a leading edge, a trailing edge, and a level of each of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data, the interrupt encoder means comprising means for detecting at least one of the leading edge, the trailing edge, and the level of each of the interrupt signals in synchronism with interrupt decode means by detecting an idle cycle;

serial transfer means for transferring the serial data; and

interrupt decoder means for converting the serial data transferred by said serial transfer means into the parallel interrupt signals to said interrupt controller, the interrupt decoder means comprising means for generating the idle cycle.

18. A system according to claim 17, wherein said interrupt decoder means comprises means for generating an idle cycle;

and said interrupt encoder means comprises;

means for generating latch pulses used for said interrupt encoder means to detect the leading edges of the interrupt signals by detecting the idle cycle; and

means for detecting at least one of the leading edge, the trailing edge, and the level of each of the interrupt signals in response to the latch pulses.

19. A system according to claim 17, wherein the idle cycle consists of a cycle for attaining synchronization, and cycles corresponding in number to the interrupt signals, the cycle for attaining synchronization is driven to active level by said interrupt decoder means, and the remaining cycles are driven by said interrupt-decoder means to non-active level.

20. A system according to claim 19, wherein said interrupt encoder means comprises means for converting the interrupt signals into serial data by driving to active level the cycles corresponding to the interrupt signals each in which at least one of the leading edge, the trailing edge, and the level is detected.

21. A system according to claim 17, wherein said interrupt decoder means comprises means which are arranged in correspondence with the number of the interrupt signals, and independently detect at least one of the leading edge, the trailing edge, and the level in units of interrupt signals.

22. A system according to claim 17, wherein said interrupt decoder means comprises:

means for generating an internal interrupt request signal to said interrupt controller on the basis of at least one of leading edge information, trailing edge information, and level information supplied from said interrupt encoder means; and

means for canceling the internal interrupt request signal in synchronism with a timing at which said interrupt controller latches the internal interrupt request signal.

23. A system according to claim 17, wherein said serial transfer means comprises a clock signal line and a serial data line.

24. A system according to claim 17, wherein said interrupt encoder means and said interrupt decoder means comprise means for selecting an edge mode or a level mode in units of interrupt signals.

25. A system according to claim 17, wherein said interrupt encoder means comprises means for distinguishing a High period of a clock signal from a Low period of the clock signal, and converting the leading edges, the trailing edges, and the levels of the interrupt signals by driving the serial data to High or Low in correspondence with the High or Low period.

26. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting level transitions of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data;

first serial transfer means for transferring the serial data;

interrupt decoder means for converting the serial data transferred by said first serial transfer means into the parallel interrupt signals, and supplying the parallel interrupt signals to said interrupt controller, the interrupt decoder means comprising means for generating an idle cycle of said first serial transfer means;

an expansion device which is connected to said computer system and generates an interrupt signal;

second serial transfer means for transferring serial data corresponding to the interrupt signal output from said expansion device to said interrupt decoder means; and

bus bridge control means for relaying between said first and second serial transfer means, including relaying the serial data transferred via said second serial transfer means to said first serial transfer means, the bus bridge control means comprising means for generating an idle cycle earlier by a predetermined number of cycles than the idle cycle of said first serial transfer means on the basis of the idle cycle of said first serial transfer means, and outputting the generated idle cycle to said second serial transfer means.

27. A system according to claim 26, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

28. A system according to claim 26, further comprising a local bus connected to said interrupt controller and an external bus connected to said expansion device, and wherein said first serial transfer means for transferring the serial data from said interrupt encoder means to said interrupt decoder means comprises a first special-purpose serial signal line independent from said local bus, said second transfer means for transferring the serial data from said expansion device to said interrupt decoder means comprises a second special-purpose serial line independent from said external bus, and said bus bridge means has a relay function of relaying between said first and second special-purpose serial lines.

29. A system according to claim 28, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

30. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting leading edges and trailing edges of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data;

first serial transfer means for transferring the serial data;

interrupt decoder means for converting the serial data transferred by said first serial transfer means into the parallel interrupt signals, and supplying the parallel interrupt signals to said interrupt controller;

an expansion device which is connected to said computer system and generates an interrupt signal;

second serial transfer means for transferring serial data corresponding to the interrupt signal output from said expansion device to said interrupt decoder means; and

bus bridge control means for relaying between said first and second serial transfer means, including relaying the serial data transferred via said second serial transfer means to said first serial transfer means, the bus bridge control means comprising means for generating an idle cycle earlier than the idle cycle of said first serial transfer means on the basis of the idle cycle of said first serial transfer means, and outputting the generated idle cycle to said second serial transfer means.

31. A system according to claim 30, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

32. A system according to claim 30, further comprising a local bus connected to said interrupt controller and an external bus connected to said expansion device, and wherein said first serial transfer means for transferring the serial data from said interrupt encoder means to said interrupt decoder means comprises a first special-purpose serial signal line independent from said local bus, said second transfer means for transferring the serial data from said expansion device to said interrupt decoder means comprises a second special-purpose serial line independent from said external bus, and said bus bridge means has a relay function of relaying between said first and second special-purpose serial lines.

33. A system according to claim 32, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

34. An interrupt control system for a computer system which comprises a processor, interrupt generation means for generating an interrupt request signal, and an interrupt controller for receiving a plurality of interrupt signals and recognizing pre-assigned functions in units of interrupt signals, comprising:

interrupt encoder means for detecting at least one of a leading edge, a trailing edge, and a level of each of parallel interrupt signals supplied from said interrupt generation means to said processor and converting the interrupt signals into serial data;

first serial transfer means for transferring the serial data;

interrupt decoder means for converting the serial data transferred by said first serial transfer means into the parallel interrupt signals, and supplying the parallel interrupt signals to said interrupt controller, the interrupt decoder means comprising means for generating an idle cycle of said first serial transfer means;

an expansion device which is connected to said computer system and generates an interrupt signal;

second serial transfer means for transferring serial data corresponding to the interrupt signal output from said expansion device to said interrupt decoder means; and

bus bridge control means for relaying between said first and second serial transfer means, including relaying the serial data transferred via said second serial transfer means to said first serial transfer means, the bus bridge control means comprising means for generating an idle cycle earlier by a predetermined number of cycles than the idle cycle of said first serial transfer means on the basis of the idle cycle of said first serial transfer means, and outputting the generated idle cycle to said second serial transfer means.

35. A system according to claim 34, wherein said interrupt encoder means and said interrupt decoder means comprise means for selecting an edge mode or a level mode in units of interrupt signals.

36. A system according to claim 34, wherein said interrupt encoder means comprises means for distinguishing a High period of a clock signal from a Low period of the clock signal, and converting the leading edges, the trailing edges, and the levels of the interrupt signals by driving the serial data to High or Low in correspondence with the High or Low period.

37. A system according to claim 34, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.

38. A system according to claim 34, further comprising a local bus connected to said interrupt controller and an external bus connected to said expansion device, and wherein said first serial transfer means for transferring the serial data from said interrupt encoder means to said interrupt decoder means comprises a first special-purpose serial signal line independent from said local bus, said second transfer means for transferring the serial data from said expansion device to said interrupt decoder means comprises a second special-purpose serial line independent from said external bus, and said bus bridge means has a relay function of relaying between said first and second special-purpose serial lines.

39. A system according to claim 38, wherein said interrupt encoder means and said interrupt decoder means comprise means for selecting an edge mode or a level mode in units of interrupt signals.

40. A system according to claim 38, wherein said interrupt encoder means comprises means for distinguishing a high period of a clock signal from a low period of the clock signal, and converting the leading edges, the trailing edges, and the levels of the interrupt signals by driving the serial data to high or low in correspondence with the high or low period.

41. A system according to claim 38, wherein said serial transfer means comprises a bus consisting of a serial clock line and a serial data line, and a plurality of said interrupt encoder means are connected to the bus.