Macrocell having a dual purpose input register for use in a logic device
First Claim
1. A macrocell of a programmable logic device, comprising a register configurable to operate as:
- (a) an input register for registering a signal received at a pin coupled to the macrocell and to be routed to a programmable interconnect matrix, the macrocell further comprising a combinatorial signal path for a signal received from the programmable interconnect matrix to be routed back thereto directly from the macrocell at the same time that the registered signal is routed to the programmable interconnect matrix;
(b) a register for a signal received from the programmable interconnect matrix, the macrocell further comprising a path to the programmable interconnect matrix for an input signal received at the pin in such a configuration; and
(c) an output register for an output signal received from the programmable interconnect matrix to be routed to the pin, the macrocell further comprising an input signal path to the programmable interconnect matrix fro the pin in such a configuration.
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Abstract
The macrocell is configured to allow a single register to be employed either as a register for storing internal macrocell product terms (or logical combinatorial thereof) or as an input register for directly storing signals received from an input/output pin. One embodiment of the macrocell, described herein, includes the register and the input/output pin, along with three two-to-one multiplexers and an output enable logic unit. Feedback lines are also provided. The components are interconnected and appropriate multiplexer and output enable selection signals are provided to allow the macrocell to input and output a variety of combinations of signals including combinatorial and registered logic signals, buried combinatorial and buried registered logic signals, and input and output signals. In one exemplary mode, the macrocell is controlled to store an input signal in the register with the output signal of this register routed to one of the feedback lines while also providing a buried combinatorial feedback path from the macrocell logic line input onto another of the feedback lines. Contents of the register may be output from the macrocell to the input/output pin or fedback along one of the feedback lines to other components of a device containing the macrocell such as a programmable interconnect matrix of a complex programmable logic device. Method and apparatus embodiments of the invention are provided.
90 Citations
20 Claims
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1. A macrocell of a programmable logic device, comprising a register configurable to operate as:
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(a) an input register for registering a signal received at a pin coupled to the macrocell and to be routed to a programmable interconnect matrix, the macrocell further comprising a combinatorial signal path for a signal received from the programmable interconnect matrix to be routed back thereto directly from the macrocell at the same time that the registered signal is routed to the programmable interconnect matrix; (b) a register for a signal received from the programmable interconnect matrix, the macrocell further comprising a path to the programmable interconnect matrix for an input signal received at the pin in such a configuration; and (c) an output register for an output signal received from the programmable interconnect matrix to be routed to the pin, the macrocell further comprising an input signal path to the programmable interconnect matrix fro the pin in such a configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A macrocell for a logic device, comprising:
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a first multiplexer selecting one of a first group of signals including a logic signal and an input/output pin signal to provide a register input signal; a register receiving (i) said register input signal and (ii) a clock signal, said register generating a register output signal in response thereto; an output buffer providing an enabled output signal to an input/output pin in response to (i) a first feedback signal and (ii) an enable signal, said first feedback signal being selected from a group of signals including said logic signal and said register output signal; a first feedback path providing said first feedback signal as a first macrocell output, said first macrocell output differing from said enabled output signal; and a second feedback path comprising a second multiplexer that selects one of a third group of signals as a second macrocell output, said third group of signals including at least two of said enabled output signal, said logic signal and said register output signal, said second macrocell output differing from said enabled output signal, wherein said macrocell may be configured to simultaneously output the logic signal and the register output signal on the first and second feedback paths. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification