System and method for sharing a non-volatile memory element as a boot device

• US 5,848,367 A
• Filed: 09/13/1996
• Issued: 12/08/1998
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Original Assignee: Sony Transcom Incorporated (Rockwell International Corporation), Sony Corporation (Sony Group Corp.)
• Inventors: Batterberry, Troy D., Lotocky, Daniel A., Atkinson, Michael R.
• Primary Examiner(s): Zanelli, Michael
• Assistant Examiner(s): Pipala, Edward J.
• Application Number:
  US08/713,874
• Time in Patent Office: 816 Days
• Field of Search: 701/33, 701/36, 701/49, 364/131-134, 348/13, 348/6, 348/7, 348/12, 395/728, 395/729, 395/200.3, 395/200.38, 395/200.42, 395/200.43, 395/200.47, 395/200.5, 395/200.52, 395/200.83
• US Class Current: 701/36
• CPC Class Codes: G06F 11/1417 Boot up procedures

Abstract

A system and method for multiple processors operating independently from one another to share memory as a boot device. The system includes a plurality of computing systems each including a processor and a local memory element. In response to a boot condition for a selected computing system, its processor begins a boot sequence in which it uses operational code contained within a non-volatile memory element that is shared by each of the computing systems. Arbitration for ownership of a memory bus interconnecting the non-volatile memory element to the processors and organization of a direct memory access transfer between the non-volatile memory element and local memory associated with the processor of the selected computing system is controlled by a memory access coordination circuit coupled between the computing systems and the memory bus.

Claims

1. A digital entertainment system implemented within a vehicle having at least one peripheral device associated with individual passenger seats within the vehicle, the digital entertainment system comprising:

a headend control system to transmit information in a first digital format;

a bridge circuit coupled to said headend control system, said bridge circuit to receive the information in the first digital format, to convert the information into a second digital format, and to output the information in the second digital format; and

a plurality of seat electronics units coupled to the bridge circuit, each of said plurality of seat electronics units including

a memory bus,

a non-volatile memory element coupled to the memory bus, said non-volatile memory element contains operational code used during a boot sequence,

a plurality of computing systems uniquely controlling operations of at least one peripheral device associated with a passenger seat, each computer system including a processor and a local memory element, to perform the boot sequence in response to a boot condition, and

a memory access coordination circuit coupled to the memory bus and to each of the plurality of computing systems, said memory access coordination circuit to control arbitration of the memory bus and to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with the selected processor.

2. The digital entertainment system according to claim 1, wherein the non-volatile memory element includes flash memory.

3. The digital entertainment system according to claim 1, wherein the memory access coordination circuit includes a micro-controller to control set-up of the direct memory access transfer.

4. The digital entertainment system according to claim 3, wherein the memory access coordination circuit further includes a storage element coupled to the micro-controller, said storage element contains code executed by the micro-controller to set-up the direct memory access transfer.

5. The digital entertainment system according to claim 4, wherein the storage element of the memory access coordination circuit further contains information pertaining to a seat configuration of the vehicle.

6. The digital entertainment system according to claim 3, wherein the memory access coordination circuit further including:

a first bus;

a second bus coupled to the micro-controller;

a first bus interface unit coupled to both the plurality of computing systems and the first bus;

a plurality of message buffers coupled to the first bus;

a plurality of pre-fetch buffers coupled to the first bus;

a plurality of control registers coupled to the first bus; and

a second bus interface unit coupled to the first bus and the second bus.

7. The digital entertainment system according to claim 6, wherein the plurality of message buffers of the memory access coordination circuit includes a send message buffer and a receive message buffer dedicated to each of the plurality of computing systems, said plurality of message buffers control communications between the selected processor and the micro-controller.

8. The digital entertainment system according to claim 7, wherein the plurality of pre-fetch buffers of the memory access coordination circuit are used to reduce loading on the second bus by supporting data bursts during the direct memory access transfer.

9. The digital entertainment system according to claim 8, wherein the plurality of control registers of the memory access coordination circuit are used to contain parameters needed to perform the direct memory access transfer.

10. The digital entertainment system according to claim 1, wherein the memory access coordination circuit includes:

a first bus;

a first bus interface unit coupled to both the plurality of computing systems and the first bus;

a plurality of pre-fetch buffers coupled to the first bus;

a plurality of control registers coupled to the first bus; and

a plurality of register sets coupled to the first bus, each of the register sets uniquely corresponding to one of the plurality of computing systems and including information needed by the plurality of control registers to set up the direct memory access transfer.

11. A circuit that controls propagation of data to at least one peripheral device placed within a vehicle, the circuit comprising:

a memory bus;

a non-volatile memory element coupled to the memory bus, said non-volatile memory element to contain operational code used during a boot sequence;

a plurality of computing systems each including a processor and a local memory element, each of the plurality of computing systems to perform the boot sequence in response to a boot condition; and

a memory access coordination circuit coupled to the memory bus and to the plurality of computing systems, said memory access coordination circuit to control a direct memory access transfer of the operational code from the non-volatile memory element to the local memory element associated with a selected processor of one of the computer systems.

12. The circuit according to claim 11, wherein the memory access coordination circuit further controlling arbitration of the memory bus during the boot sequence to award ownership to the selected processor.

13. The circuit according to claim 11, wherein the non-volatile memory element includes flash memory.

14. The circuit according to claim 12, wherein the memory access coordination circuit includes a micro-controller to control set-up of the direct memory access transfer.

15. The circuit according to claim 14, wherein the memory access coordination circuit further includes a storage element coupled to the micro-controller, said storage element contains code executed by the micro-controller to set-up the direct memory access transfer.

16. The circuit according to claim 15, wherein the storage element of the memory access coordination circuit further contains information pertaining to a seat configuration of the vehicle.

17. The circuit according to claim 14, wherein the memory access coordination circuit further including:

a first bus;

a second bus coupled to the micro-controller;

a first bus interface unit coupled to both the plurality of computing systems and the first bus;

a plurality of message buffers coupled to the first bus;

a plurality of pre-fetch buffers coupled to the first bus;

a plurality of control registers coupled to the first bus; and

a second bus interface unit coupled to the first bus and the second bus.

18. The circuit according to claim 17, wherein the plurality of message buffers of the memory access coordination circuit includes a send message buffer and a receive message buffer dedicated to each of the plurality of computing systems, said plurality of message buffers control communications between the selected processor and the micro-controller.

19. The circuit according to claim 18, wherein the plurality of pre-fetch buffers of the memory access coordination circuit are used to reduce loading on the second bus by supporting data bursts during the direct memory access transfer.

20. The circuit according to claim 19, wherein the plurality of control registers of the memory access coordination circuit are used to contain parameters needed to perform the direct memory access transfer.

21. The circuit according to claim 11, wherein the memory access coordination circuit includes:

a first bus;

a first bus interface unit coupled to both the plurality of computing systems and the first bus;

a plurality of pre-fetch buffers coupled to the first bus;

a plurality of control registers coupled to the first bus; and

a plurality of register sets coupled to the first bus, each of the register sets uniquely corresponding to one of the plurality of computing systems and including information needed by the plurality of control registers to set up the direct memory access transfer.

22. A method for performing a boot sequence by obtaining operational code from a memory element of which its contents are shared by a plurality of processors, the method comprising the steps of:

determining that a boot condition exists in at least one processor of the plurality of processors;

preparing for a direct memory access transfer from the memory element to a memory local to the at least one processor;

requesting ownership of the memory bus for transferring operational code into the memory local to the at least one processor; and

performing the direct memory access transfer of operational code from the memory element into the memory local to the at least one processor.

23. The method of claim 22, wherein the performing step occurs after receiving a grant of ownership of the memory bus.

24. The method of claim 22, wherein the preparing step includes the steps of:

providing a section index to a microcontroller.

25. The method of claim 24, wherein the providing step includes the steps of

sending a pre-formatted message into a first buffer, the message includes the section index;

interrupting the micro-controller to indicate the message is in the first buffer; and

reading the message by the micro-controller to determine a starting address of the direct memory access transfer.