Address protection circuit and method for preventing access to unauthorized address rangers
First Claim
1. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:
- (a) an address comparison means for comparing a memory address request from a requesting address source to a set of predefined authorization codes corresponding to address ranges in the addressable memory;
(b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request from the requesting address source corresponding to at least one of the predefined authorization codes; and
(c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory.
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Accused Products
Abstract
An address protection circuit (APC) for cross-checking the integrity of requests to read or write an addressable system memory in a fault-tolerant computer system. In a check mode, the APC checks each address and a source identification code of each memory access request from an address source. The source identification code and current bus address are compared to a range of addresses stored in the APC. If the current bus address is within an "authorized" range, access to that range of locations in the memory is allowed to the address source. If a current memory access request is not authorized, the APC asserts an error signal which may be used to transfer control to a redundant subsystem. The APC contains a content-addressable memory element that can be initialized by a subsystem processor with address ranges and type of access (e.g., read or write) allowed for each source. To enter the setup mode, the APC must first be addressed to switch the APC from its check mode. Thereafter, only a single value in the APC can be changed by the processor. The APC then automatically reverts to its check mode. Further changes to values in the APC each require an explicit switch from the check mode to the setup mode.
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Citations
106 Claims
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1. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:
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(a) an address comparison means for comparing a memory address request from a requesting address source to a set of predefined authorization codes corresponding to address ranges in the addressable memory; (b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request from the requesting address source corresponding to at least one of the predefined authorization codes; and (c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory. - View Dependent Claims (2, 3, 4, 5, 11, 12)
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6. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:
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(a) a data storage means for storing at least one authorization code for a corresponding address range in the addressable memory, (b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt from a requesting address source of a memory address request corresponding to a stored authorization code; and (c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory. - View Dependent Claims (7, 8, 9, 10)
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13. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit comprising:
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(a) an address checking circuit, for generating and transmitting an access authorization signal to the protected addressable memory upon receipt of an authorized memory address request from a requesting address source and (b) a communication pathway coupled to the requesting address source and the protected addressable memory, the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the protected addressable memory.
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14. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:
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(a) content addressable storage means, (1) for storing at least one authorization code for a corresponding address range in the addressable memory, and (2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a regulating address source to enable the requesting address source to directly access the protected addressable memory; (b) programming means, coupled to the content addressable storage means, for selectively programming each authorization code within the content addressable storage means; wherein each memory address request includes at set of memory address signals and a source identification code identifying a requesting address source. - View Dependent Claims (15)
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16. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, the address protection circuit including:
(a) a content addressable storage device for; (1) storing at least one authorization code for a corresponding address range in the addressable memory; and (2) generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source;
wherein each memory address request includes a set of memory address signals and a source identification code identifying a requesting address source;
wherein a communication pathway is coupled to the requesting address source and the addressable memory such that the communication pathway bypasses the processing unit, and wherein the communication pathway communicates data between the requesting address source and the addressable memory.- View Dependent Claims (17, 18)
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19. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:
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(a) content addressable random access memory means for; (1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and (2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to one of the stored authorization codes from an address source to enable the requesting address source to directly access the protected addressable memory; (b) multiplexing means, coupled to the content addressable random access memory means, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory means; (c) first programmable array logic means, coupled to the content addressable random access memory means, for preventing access to the protected addressable memory when any one of the following conditions occur; (1) an address request is attempted at an address is outside a predetermined range of addresses; (2) a disable signal is asserted;
or(3) the access authorization signal is not asserted, (d) second programmable array logic means, coupled to the first programmable array logic means, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory means, and the disable signal to the first programmable array logic means; (e) third programmable array logic means, coupled to the second programmable array logic means, for generating and transmitting to the content addressable random access memory means, a content addressable random access memory select signal upon detection by the third programmable array logic means of a predetermined key.
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20. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:
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(a) content addressable storage means; (1) for storing at least one authorization code for a corresponding address range in the addressable memory, and; (2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source; (b) means, coupled to the content addressable storage means, for transmitting the generated access authorization signal to the requesting address source upon receipt of a memory address request from the requesting address source; wherein each memory address request from the address source includes a set of memory address signals and a source identification code identifying a requesting address source.
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21. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:
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(a) content addressable storage means, coupled to at least one address source and to the protected addressable memory; (1) for storing at least one authorization code for a corresponding address range in the protected addressable memory; and (2) for generating and transmitting an access authorization signal to the protected addressable memory upon receipt of d memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory; (b) programming means, coupled to the content addressable storage means for selectively programming each authorization code, and including a means for limiting access to the programming means to preselected address sources; and (c) disabling means, coupled to the content addressable storage means, for preventing the transmittal of the access authorization signal to the protected addressable memory; wherein each memory address request includes a set of addressable memory address signals, a source identification code identifying the requesting address source, and a signal selectively identifying a read or write operation.
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22. A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:
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(a) receiving memory address requests from a requesting address source; (b) generating and transmitting an access approval signal to the addressable memory upon receipt of a valid memory address request from the requesting address source, (c) receiving the access approval by the addressable memory; (d) communicating data between the requesting address source and the addressable memory; and (e) bypassing the processing unit when performing step (d).
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23. A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:
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(a) receiving memory address requests from at least one address source; (b) comparing each received memory address request to a set of predefined authorization codes corresponding to address ranges in the addressable memory a (c) generating and transmitting the access authorization signal to the addressable memory upon receipt of a memory address request corresponding to at least one of the predefined authorization codes, (d) receiving the access approval by the addressable memory; (e) communicating data between the requesting address source and the addressable memory and (f) bypassing the processing unit when performing step (e). - View Dependent Claims (24, 25, 26, 27)
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28. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:
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(a) a content addressable random access memory for; (1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and (2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory; (b) a multiplexer, coupled to the content addressable random access memory, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory; (c) first programmable array logic circuit, coupled to the content addressable random access memory circuit, for preventing access to the protected addressable memory when any one of the following conditions occur; (1) an address request is attempted at an address outside a predetermined range of addresses; (2) a disable signal is asserted;
or(3) the access authorization signal is not asserted, (d) second programmable array logic circuit, coupled to the first programmable array logic circuit, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory, and the disable signal to the first programmable array logic circuit; (e) third programmable array logic circuit, coupled to the second programmable array logic circuit, for generating and transmitting to the content addressable random access memory, a content addressable random access memory select signal upon detection by the third programmable array logic circuit of a predetermined key.
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29. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:
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(a) a content addressable storage device for; (1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and (2) generating and transmitting an access authorization signal to the protected, addressable memory upon receipt of a memory address request corresponding to a stored authorization code to enable the requesting address source to directly access the protected addressable memory; (b) a programming circuit, coupled to the content addressable storage device, for selectively programming each authorization code, and including a security checking circuit for limiting access to the programming circuit to preselected address sources; and (c) a disabling circuit, coupled to the content addressable storage device, for preventing the transmittal of the access authorization signal to the protected addressable memory; wherein each memory address request from the address source includes a set of addressable memory address signals, a source identification code identifying a requesting address source, and a signal selectively identifying a read or write operation.
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30. A circuit for detecting an erroneous memory address request from an address source to an addressable memory comprising:
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an authorization code memory for storing an authorization code for an address range in the addressable memory to which said address source is permitted access; a bus connected to apply an address and a source identification code from said address source to the authorization code memory, wherein said authorization code memory produces an affirmative authorization code only if the applied address is within the permitted address range of the address source; and an access signal generator for providing an access signal to enable said address source to access said addressable memory in response to the affirmative authorization code. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
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55. A data processing system having an addressable memory, a processor address source, and at least another address source, each of said address sources providing an address to said addressable memory and a source identification code, and a bus for delivering at least said addresses to said addressable memory, comprising:
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an address protection circuit coupled to receive said addresses and said source identification codes from said address sources; said address protection circuit producing an affirmative authorization signal to the addressable memory upon receipt of an authorized memory address request from either said processor address source or said another address source. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73)
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74. An address protection circuit for detecting erroneous memory address requests from each of a plurality of address sources to an addressable memory, the address protection circuit including:
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(a) a content addressable memory for storing an authorization code for each of said address sources, and for producing said authorization code when a memory access request is made to the content addressable memory by any one of said address sources, said memory access request including an address and an address source identification code that indicates whether said address is within a range of addresses authorized to said one of said address sources; (b) and a circuit for providing an access authorization signal to the addressable memory according to said authorization code. - View Dependent Claims (75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90)
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91. A method for detecting erroneous memory address requests from an address source to an addressable memory, comprising the steps of:
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receiving memory address requests from the address source; and providing an access authorization signal to the addressable memory upon receipt of a valid memory address request from the address source. - View Dependent Claims (92)
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93. A method for detecting erroneous memory address requests from an address source to an addressable memory in a redundant computer system, comprising the steps of:
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receiving memory address requests from the address source; providing a predefined authorization code corresponding to an authorized address range for said address source in the addressable memory; and providing an access authorization signal to the addressable memory selectively according to said authorization code upon receipt of a memory address request from said address source. - View Dependent Claims (94, 95, 96, 97, 98)
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99. An address protection circuit for detecting erroneous memory access requests from at least one address source to a protected memory, comprising:
an address checking circuit connected to receive a memory access request from said at least one address source for providing a no-access signal to the protected addressable memory if said memory access request is not within an address range of said protected memory that is authorized to said at least one address source. - View Dependent Claims (100, 101, 102, 103, 104, 105, 106)
Specification