Address protection circuit and method for preventing access to unauthorized address rangers

• US 5,848,435 A
• Filed: 10/23/1995
• Issued: 12/08/1998
• Est. Priority Date: 10/19/1990
• Status: Expired due to Term

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Brant, William Alexander, Tang, Edde Tin-Shek
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/551,928
• Time in Patent Office: 1,142 Days
• Field of Search: 711/152, 711/163, 711/164
• US Class Current: 711/152
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1441 for a range

Abstract

An address protection circuit (APC) for cross-checking the integrity of requests to read or write an addressable system memory in a fault-tolerant computer system. In a check mode, the APC checks each address and a source identification code of each memory access request from an address source. The source identification code and current bus address are compared to a range of addresses stored in the APC. If the current bus address is within an "authorized" range, access to that range of locations in the memory is allowed to the address source. If a current memory access request is not authorized, the APC asserts an error signal which may be used to transfer control to a redundant subsystem. The APC contains a content-addressable memory element that can be initialized by a subsystem processor with address ranges and type of access (e.g., read or write) allowed for each source. To enter the setup mode, the APC must first be addressed to switch the APC from its check mode. Thereafter, only a single value in the APC can be changed by the processor. The APC then automatically reverts to its check mode. Further changes to values in the APC each require an explicit switch from the check mode to the setup mode.

Claims

1. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:

(a) an address comparison means for comparing a memory address request from a requesting address source to a set of predefined authorization codes corresponding to address ranges in the addressable memory;

(b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request from the requesting address source corresponding to at least one of the predefined authorization codes; and

(c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory.

2. The address protection circuit of claim 1, further including disabling means, coupled to the address comparison means, for preventing the transmittal of the access authorization signal to the addressable memory.

3. The address protection circuit of claim 1, further including programming means, coupled to the address comparison means, for selectively programming each of the predefined authorization codes within the data storage means.

4. The address protection circuit of claim 3, wherein the programming means includes security checking means for limiting access to the programming means to preselected address sources.

5. The address protection circuit of claim 3, wherein the programming means is coupled to a first bus means and the address comparison means is coupled to a second bus means.

11. The address protection circuit of claims 1, or 6, wherein each memory address request includes a set of memory address signals and a source identification code identifying a requesting address source.

12. The address protection circuit of claim 11, wherein each memory address request further includes a signal selectively identifying a read or write operation.

6. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:

(a) a data storage means for storing at least one authorization code for a corresponding address range in the addressable memory,

(b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt from a requesting address source of a memory address request corresponding to a stored authorization code; and

(c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory.

7. The address protection circuit of claim 6, wherein the data storage means is content addressable.

8. The address protection circuit of claim 6, further including disabling means, coupled to the data storage means, for preventing the transmittal of the access authorization signal to the addressable memory.

9. The address protection circuit of claim 6, further including programming means, coupled to the data storage means, for selectively programming each stored authorization code within the data storage means.

10. The address protection circuit of claims 9 wherein the programming means includes means for limiting access to the programming means to a preselected address source.

13. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit comprising:

(a) an address checking circuit, for generating and transmitting an access authorization signal to the protected addressable memory upon receipt of an authorized memory address request from a requesting address source and

(b) a communication pathway coupled to the requesting address source and the protected addressable memory, the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the protected addressable memory.

14. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:

(a) content addressable storage means,

(1) for storing at least one authorization code for a corresponding address range in the addressable memory, and

(2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a regulating address source to enable the requesting address source to directly access the protected addressable memory;

(b) programming means, coupled to the content addressable storage means, for selectively programming each authorization code within the content addressable storage means;

wherein each memory address request includes at set of memory address signals and a source identification code identifying a requesting address source.

15. The address protection circuit of claim 14, wherein the programming means includes security checking means for limiting access to the programming means to preselected coupled address sources.

16. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, the address protection circuit including:

(a) a content addressable storage device for;

(1) storing at least one authorization code for a corresponding address range in the addressable memory; and

(2) generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source;

wherein each memory address request includes a set of memory address signals and a source identification code identifying a requesting address source;

wherein a communication pathway is coupled to the requesting address source and the addressable memory such that the communication pathway bypasses the processing unit, and wherein the communication pathway communicates data between the requesting address source and the addressable memory.

17. The address protection circuit of claim 16, wherein each memory address request further includes a signal selectively identifying a read or write operation.

18. The address protection circuit of claim 16, further including disabling means, coupled to the content addressable storage device, for preventing the transmittal of the access authorization signal to the addressable memory.

19. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

(a) content addressable random access memory means for;

(1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and

(2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to one of the stored authorization codes from an address source to enable the requesting address source to directly access the protected addressable memory;

(b) multiplexing means, coupled to the content addressable random access memory means, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory means;

(c) first programmable array logic means, coupled to the content addressable random access memory means, for preventing access to the protected addressable memory when any one of the following conditions occur;

(1) an address request is attempted at an address is outside a predetermined range of addresses;

(2) a disable signal is asserted;

or

(3) the access authorization signal is not asserted,

(d) second programmable array logic means, coupled to the first programmable array logic means, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory means, and the disable signal to the first programmable array logic means;

(e) third programmable array logic means, coupled to the second programmable array logic means, for generating and transmitting to the content addressable random access memory means, a content addressable random access memory select signal upon detection by the third programmable array logic means of a predetermined key.

20. An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:

(a) content addressable storage means;

(1) for storing at least one authorization code for a corresponding address range in the addressable memory, and;

(2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source;

(b) means, coupled to the content addressable storage means, for transmitting the generated access authorization signal to the requesting address source upon receipt of a memory address request from the requesting address source;

wherein each memory address request from the address source includes a set of memory address signals and a source identification code identifying a requesting address source.

21. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

(a) content addressable storage means, coupled to at least one address source and to the protected addressable memory;

(1) for storing at least one authorization code for a corresponding address range in the protected addressable memory; and

(2) for generating and transmitting an access authorization signal to the protected addressable memory upon receipt of d memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory;

(b) programming means, coupled to the content addressable storage means for selectively programming each authorization code, and including a means for limiting access to the programming means to preselected address sources; and

(c) disabling means, coupled to the content addressable storage means, for preventing the transmittal of the access authorization signal to the protected addressable memory;

wherein each memory address request includes a set of addressable memory address signals, a source identification code identifying the requesting address source, and a signal selectively identifying a read or write operation.

22. A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:

(a) receiving memory address requests from a requesting address source;

(b) generating and transmitting an access approval signal to the addressable memory upon receipt of a valid memory address request from the requesting address source,

(c) receiving the access approval by the addressable memory;

(d) communicating data between the requesting address source and the addressable memory; and

(e) bypassing the processing unit when performing step (d).

23. A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:

(a) receiving memory address requests from at least one address source;

(b) comparing each received memory address request to a set of predefined authorization codes corresponding to address ranges in the addressable memory a

(c) generating and transmitting the access authorization signal to the addressable memory upon receipt of a memory address request corresponding to at least one of the predefined authorization codes,

(d) receiving the access approval by the addressable memory;

(e) communicating data between the requesting address source and the addressable memory and

(f) bypassing the processing unit when performing step (e).

24. The method for detecting erroneous memory address requests of claim 23, further including the step of selectively programming each of the predefined authorization codes.

25. The method for detecting erroneous memory address requests of claim 23, further including the step of selectively preventing the transmittal of the access authorization signal to the addressable memory upon receipt of a memory address request which does not correspond to at least one of the predefined authorization codes.

26. The method for detecting erroneous memory address requests of claim 24, further including the step of limiting the ability to change each of the predefined authorization codes to a preselected address source.

27. The method of claim 24, further including the step of subsequently changing one or more of the authorization codes.

28. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

(a) a content addressable random access memory for;

(1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and

(2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory;

(b) a multiplexer, coupled to the content addressable random access memory, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory;

(c) first programmable array logic circuit, coupled to the content addressable random access memory circuit, for preventing access to the protected addressable memory when any one of the following conditions occur;

(1) an address request is attempted at an address outside a predetermined range of addresses;

(2) a disable signal is asserted;

or

(3) the access authorization signal is not asserted,

(d) second programmable array logic circuit, coupled to the first programmable array logic circuit, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory, and the disable signal to the first programmable array logic circuit;

(e) third programmable array logic circuit, coupled to the second programmable array logic circuit, for generating and transmitting to the content addressable random access memory, a content addressable random access memory select signal upon detection by the third programmable array logic circuit of a predetermined key.

29. An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

(a) a content addressable storage device for;

(1) storing at least one authorization code for a corresponding address range in the protected addressable memory; and

(2) generating and transmitting an access authorization signal to the protected, addressable memory upon receipt of a memory address request corresponding to a stored authorization code to enable the requesting address source to directly access the protected addressable memory;

(b) a programming circuit, coupled to the content addressable storage device, for selectively programming each authorization code, and including a security checking circuit for limiting access to the programming circuit to preselected address sources; and

(c) a disabling circuit, coupled to the content addressable storage device, for preventing the transmittal of the access authorization signal to the protected addressable memory;

wherein each memory address request from the address source includes a set of addressable memory address signals, a source identification code identifying a requesting address source, and a signal selectively identifying a read or write operation.

30. A circuit for detecting an erroneous memory address request from an address source to an addressable memory comprising:

an authorization code memory for storing an authorization code for an address range in the addressable memory to which said address source is permitted access;

a bus connected to apply an address and a source identification code from said address source to the authorization code memory, wherein said authorization code memory produces an affirmative authorization code only if the applied address is within the permitted address range of the address source;

and an access signal generator for providing an access signal to enable said address source to access said addressable memory in response to the affirmative authorization code.

31. The address protection circuit of claim 30 wherein said address source is an address source/other than a processor.

32. The address protection circuit of claim 30 wherein said address source is an I/O circuit.

33. The address protection circuit of claim 30 wherein said address source is a disk controller circuit.

34. The address protection circuit of claim 30 wherein said address source is a direct memory access circuit.

35. The address protection circuit of claim 30 wherein said address source is an address source of a redundant computer system.

36. The address protection circuit of claim 30 wherein said address source is an address source of a redundant computer subsystem.

37. The address protection circuit of claim 30 wherein said authorized address range of the address source is a page in the addressable memory.

38. The address protection circuit of claim 37 wherein said page in the addressable memory has a page size of approximately 2048 bytes.

39. The address protection circuit of claim 37 wherein said page in the addressable memory has a page size of 1 byte.

40. The address protection circuit of claim 30 wherein said authorization code memory is a CAM.

41. The address protection circuit of claim 30 wherein said authorization code memory is a "look-up" table.

42. The address protection circuit of claim 30 wherein said authorization code memory is implemented by an algorithmic means.

43. The address protection circuit of claim 42 wherein said algorithmic means includes a hashing algorithm.

44. The address protection circuit of claim 30 wherein said access signal generator is a PAL.

45. The address protection circuit of claim 30 wherein said access signal generator produces a no-access signal in the absence of said affirmative authorization code, said no-access signal disabling access by said address source to said addressable memory.

46. The address protection circuit of claim 30 further comprising a programming circuit coupled to the authorization code memory for selectively defining said authorization code within said second memory.

47. The address protection circuit of claim 46 further comprising a security circuit for limiting access by the programming circuit to a preselected address source.

48. The address protection circuit of claim 47 further comprising a security circuit including a PAL and wherein the preselected address source is a processor.

49. The address protection circuit of claim 30 further comprising a disable circuit coupled to the authorization code memory for disabling the addressable memory entirely.

50. The address protection circuit of claim 30 wherein said bus includes a read/write line and wherein a read/write signal from said address source is also applied to said authorization code memory to produce said authorization code.

51. The address protection circuit of claim 30 further comprising testing circuitry coupled to the authorization code memory and to an address source for conducting the access approval signal to the address source upon receipt by the authorization code memory of a memory address request.

52. The address protection circuit of claim 30 further comprising circuitry to provide a signal to transfer functional control to another subsystem if said memory does not produce an affirmative authorization code when an address that is not within the authorized address range of the address source is applied.

53. The address protection circuit of claim 30 wherein said access signal to enable said address source to access said addressable memory comprises a plurality of related access signals to a plurality of related addressable memory locations.

54. The address protection circuit of claim 30 wherein said address protection circuit is simulated by code running on a microprocessor.

55. A data processing system having an addressable memory, a processor address source, and at least another address source, each of said address sources providing an address to said addressable memory and a source identification code, and a bus for delivering at least said addresses to said addressable memory, comprising:

an address protection circuit coupled to receive said addresses and said source identification codes from said address sources;

said address protection circuit producing an affirmative authorization signal to the addressable memory upon receipt of an authorized memory address request from either said processor address source or said another address source.

56. The data processing system of claim 55 wherein said another address source is an I/O circuit.

57. The data processing system of claim 55 wherein said another address source is an direct memory access circuit.

58. The data processing system of claim 55 wherein said another address source is a disk controller circuit.

59. The data processing system of claim 55 wherein said another address source is an address source of a redundant computer system.

60. The data processing system of claim 55 wherein said address source is an address source of a redundant computer subsystem.

61. The data processing system of claim 55 wherein said authorized memory address request is an address request within an authorized address range.

62. The data processing system of claim 55 wherein said authorized address range is a page in the addressable memory.

63. The data processing system of claim 62 wherein said page in the addressable memory has a page size of approximately 2048 bytes.

64. The data processing system of claim 62 wherein said page in the addressable memory has a page size of 1 byte.

65. The data processing system of claim 55 wherein said address protection circuit comprises a CAM to produce said affirmative authorization signal upon receipt of an authorized memory address request.

66. The data processing system of claim 55 wherein said address protection circuit comprises a "look-up" table to produce said affirmative authorization signal upon receipt of an authorized memory address request.

67. The data processing system of claim 55 wherein said address protection circuit comprises an algorithmic means to produce said affirmative authorization signal upon receipt of an authorized memory address request.

68. The data processing system of claim 67 wherein said algorithmic means includes a hashing algorithm.

69. The data processing system of claim 55 wherein said address protection circuit further comprises a circuit to produce a no-access signal in the absence of an authorized memory address request.

70. The data processing system of claim 55 wherein said processor address source, and at least another address source provide a read/write signal to said addressable memory and wherein said read/write signals are also applied to said address protection circuit to produce said affirmative authorization signal.

71. The data processing system of claim 55 further comprising circuitry to provide a signal to transfer functional control to another subsystem if said address protection circuit does not produce an affirmative authorization signal upon receipt of an authorized memory address request.

72. The data processing system of claim 55 wherein said affirmative authorization signal to the addressable memory comprises a plurality of related affirmative authorization signals to a plurality of related addressable memory locations.

73. The data processing system of claim 55 wherein said address protection circuit is simulated by code running on a microprocessor.

74. An address protection circuit for detecting erroneous memory address requests from each of a plurality of address sources to an addressable memory, the address protection circuit including:

(a) a content addressable memory for storing an authorization code for each of said address sources, and for producing said authorization code when a memory access request is made to the content addressable memory by any one of said address sources, said memory access request including an address and an address source identification code that indicates whether said address is within a range of addresses authorized to said one of said address sources;

(b) and a circuit for providing an access authorization signal to the addressable memory according to said authorization code.

75. The address protection circuit of claim 74 wherein said plurality of address sources comprises at least one address source other than a processor.

76. The address protection circuit of claim 74 wherein at least one of said address sources is an I/O circuit.

77. The address protection circuit of claim 74 wherein at least one of said address sources is a disk controller circuit.

78. The address protection circuit of claim 74 wherein at least one of said address sources is a direct memory access circuit.

79. The address protection circuit of claim 74 wherein said at least one of said address sources is an address source of a redundant computer system.

80. The address protection circuit of claim 74 wherein said at least one of said address sources is an address source of a redundant computer subsystem.

81. The address protection circuit of claim 74 wherein said range of addresses authorized to a respective one said address sources is a page in the addressable memory.

82. The address protection circuit of claim 74 wherein each of said pages in the addressable memory has a page size of approximately 2048 bytes.

83. The address protection circuit of claim 81 wherein each of said pages in the addressable memory has a page size of 1 byte.

84. The address protection circuit of claim 81 further comprising setup mode circuitry coupled to the content addressable memory and to at least one of the address sources for selectively defining said authorization code.

85. The address protection circuit of claim 84 wherein the setup mode circuitry includes a security system for limiting access to the setup mode circuitry to a preselected one of the address sources.

86. The address protection circuit of claim 84 wherein said preselected one of the address sources is a processor.

87. The address protection circuit of claim 74 wherein each memory address request further includes a read/write signal.

88. The address protection circuit of claim 74 further including a disabling circuit coupled to the content addressable memory for preventing the transmittal of the access authorization signal to the addressable memory.

89. The address protection circuit of claim 74 further comprising a tester coupled to the content addressable memory and to at least one of the address sources for transmitting the access authorization signal to said at least one of the address sources when a memory address request is made by any one of the address sources.

90. The address protection circuit of claim 74 wherein said circuit for providing an access authorization signal comprises a plurality of related access authorization signals to a plurality of related addressable memory locations.

91. A method for detecting erroneous memory address requests from an address source to an addressable memory, comprising the steps of:

receiving memory address requests from the address source; and

providing an access authorization signal to the addressable memory upon receipt of a valid memory address request from the address source.

92. The method of claim 91 wherein said access authorization signal to the addressable memory comprises a plurality of related access authorization signals to a plurality of related addressable memory locations.

93. A method for detecting erroneous memory address requests from an address source to an addressable memory in a redundant computer system, comprising the steps of:

receiving memory address requests from the address source;

providing a predefined authorization code corresponding to an authorized address range for said address source in the addressable memory; and

providing an access authorization signal to the addressable memory selectively according to said authorization code upon receipt of a memory address request from said address source.

94. The method of claim 93 further comprising selectively programming said authorization code.

95. The method of claim 93 further comprising limiting the ability to change said authorization code to a preselected address source.

96. The method of claim 93 further comprising preventing the transmittal of an affirmative access authorization signal to the addressable memory upon receipt of a memory address request outside an authorized address range.

97. The method of claim 93 further comprising changing said authorization code.

98. The method of claim 93 wherein said access authorization signal comprises a plurality of related access authorization signals to a plurality of related addressable memory locations.

99. An address protection circuit for detecting erroneous memory access requests from at least one address source to a protected memory, comprising:

an address checking circuit connected to receive a memory access request from said at least one address source for providing a no-access signal to the protected addressable memory if said memory access request is not within an address range of said protected memory that is authorized to said at least one address source.

100. The address protection circuit of claim 99 wherein said at least one address source comprises a plurality of address sources.

101. The address protection circuit of claim 99 wherein said protected memory is a memory of a redundant computer system.

102. The address protection circuit of claim 101 wherein said no-access signal transfers control to a redundant subsystem.

103. The address protection circuit of claim 99 wherein said at least one address source is a processor.

104. The address protection circuit of claim 99 wherein said at least one address source is other than a processor.

105. The address protection circuit of claim 99 wherein said at least one address source is a direct memory access circuit.

106. The address protection circuit of claim 99 wherein said address protection circuit is simulated by code running on a microprocessor.