Methods of making semiconductor chip assemblies

• US 5,848,467 A
• Filed: 05/13/1997
• Issued: 12/15/1998
• Est. Priority Date: 09/24/1990
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Khandros, Igor Y., DiStefano, Thomas H.
• Primary Examiner(s): HUGHES, SAMUEL T
• Application Number:
  US08/855,127
• Time in Patent Office: 581 Days
• Field of Search: 29/25.01, 29/831, 29/832, 29/840, 29/841, 29/842, 29/855, 257/700, 257/758, 257/750, 257/786, 257/798, 438/107, 438/108, 438/110, 438/113
• US Class Current: 29/841
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06579 : TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3164 : the coating being a foil
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49861 : Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base
• CPC Class Codes: Y10T 29/49171 : with encapsulating

Abstract

Semiconductor chip assemblies are fabricated by providing a wafer having a plurality of semiconductor chips and providing a sheet separate from the wafer having a plurality of dielectric elements. Each chip has a plurality of contacts and each dielectric element has a plurality of terminal formed thereon. The sheet and the wafer are then assembled so that the terminals on the dielectric elements face away from the wafer and so that each chip is associated with a dielectric element. The contacts on each chip are connected to the terminals on a dielectric element associated with the chip. The individual dialectic elements are then severed from the sheet and the individual chips are severed from the wafer after the assembling and connecting step to provide subassemblies, each subassembly including a chip and the dielectric element associated with the chip. In another embodiment, a plurality of individual dielectric elements separate from one another and separate from a wafer are provided.

Claims

1. A method of making a plurality of semiconductor chip assemblies comprising the steps of:

(a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon;

(b) providing a sheet separate from said wafer incorporating a plurality of dielectric elements having terminals thereon,

(c) assembling the sheet to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and

(d) severing the individual dielectric elements from the sheet and severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each said subassembly including a chip and a dielectric element associated therewith.

2. A method as claimed in claim 1 further comprising the step of encapsulating connections between said terminals and said contacts with a dielectric encapsulant prior to said severing step.

3. A method as claimed in claim 2 wherein said encapsulating step includes the step of applying said encapsulant so that the encapsulant penetrates between the dielectric elements and the chips to form a layer between the dielectric elements and the chips.

4. A method as claimed in claim 2 wherein said encapsulant is a compliant material.

5. A method of making a plurality of semiconductor chip assemblies comprising the steps of:

(a) providing a semicondutor wafer including a plurality of semiconductor chips having contacts thereon;

(b) providing a plurality of individual dielectric elements separate from one another and separate from said wafer, said dielectric elements having terminals thereon;

(c) assembling said dielectric elements to the wafer so that the terminals on said dielectic elements face away from the wafer and so that said chips are associated with said dielectric elements, and connecting contacts on said chips to terminals on the dielectric elements associated with said chips; and

(d) severing the individual chips from said wafer after said assembling and connecting step so as to provide a plurality of subassemblies, each including a chip and a dielectric element associated therewith.

6. A method as claimed in claim 5 further comprising the step of encapsulating connections between said terminals and said contacts with a dielectric encapsulant prior to said severing step.

7. A method as claimed in claim 6 wherein said encapsulating step includes the step of applying said encapsulant so that the encapsulant penetrates between the dielectric elements and the chips to form a layer between the dielectric elements and the chips.

8. A method as claimed in claim 6 wherein said encapsulant is a compliant material.