MOS poly-si thin film transistor with a flattened channel interface and method of producing same

• US 5,849,612 A
• Filed: 02/03/1997
• Issued: 12/15/1998
• Est. Priority Date: 01/17/1992
• Status: Expired due to Term

• Current Assignee: Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Takahashi, Hiroshi, Kojima, Yoshikazu
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/794,585
• Time in Patent Office: 680 Days
• Field of Search: 438/151, 438/152, 438/301, 438/303, 438/305, 438/307, 438/691, 438/692
• US Class Current: 438/151
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.

Claims

1. A method of producing a thin film field effect transistor comprising the steps of:

forming, on a backing substrate, a polycrystalline semiconductor layer having a surface, the polycrystalline semiconductor layer having a first section defining a channel region and two further sections separated from one another by the first section;

flattening the surface of the polycrystalline semiconductor layer at least at the first section;

forming an insulating layer to define a gate insulating film on the flattened surface of the polycrystalline semiconductor layer;

depositing a conductive layer to define a gate electrode on the gate insulating film; and

introducing an impurity into the two further sections of the polycrystalline semiconductor layer to form source and drain regions which are separated from one another by the channel region.

2. A method of producing a thin film field effect transistor as claimed in claim 1 wherein the step of flattening the surface comprises polishing the surface of the polycrystalline semiconductor layer.

3. A method of producing a thin film field effect transistor as claimed in claim 1 wherein the step of flattening the surface comprises depositing an insulating cap layer on the polycrystalline semiconductor layer to prevent the surface from being roughened.

4. A method of producing a thin film field effect transistor as claimed in claim 1 wherein the step of forming an insulating layer is performed by a CVD procedure.