BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip

• US 5,850,155 A
• Filed: 12/02/1996
• Issued: 12/15/1998
• Est. Priority Date: 11/30/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Matsumoto, Koji
• Primary Examiner(s): Tokar, Michael J.
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US08/758,664
• Time in Patent Office: 743 Days
• Field of Search: 326/66, 326/73, 326/77, 326/64, 326/126, 326/127, 326/109, 326/110, 327/198, 327/217, 327/199, 327/215, 327/218, 327/212
• US Class Current: 326/109
• CPC Class Codes: H03K 19/017527 with at least one differential stage
• CPC Class Codes: H03K 3/021 by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration

Abstract

A single chip IC includes a bipolar logic, a complementary metal-oxide semiconductor (CMOS) logic, and a level translator which interfaces the bipolar logic with the CMOS logic. The single chip IC comprises a MOS transistor logic, provided in the bipolar logic, for receiving a control signal which controls an operation of the bipolar logic. The control signal issues from the CMOS logic and bypasses the level translator and is applied to the MOS transistor logic.

Claims

1. A single chip integrated circuit (IC) including, a bipolar logic, a complementary metal-oxide semiconductor (CMOS) logic, and a level translator which interfaces said bipolar logic with said CMOS logic, said single chip IC comprising:

a MOS transistor logic means, combined with said bipolar logic, for receiving a control signal which controls an operation of said bipolar logic, said control signal being directly applied to said MOS transistor logic means from said CMOS.

2. A single chip IC as claimed in claim 1, wherein said bipolar logic is a pair of set/reset type latches which are arranged in tandem with each other and which each comprises:

first and second pairs of bipolar transistors, provided in parallel between power sources, for respectively receiving and latching data;

a third pair of bipolar transistors, coupled in series, between said power sources, with said first and second pairs of bipolar transistors, said third pair of bipolar transistors responding to a clock signal applied thereto and switching a first power source current path between said first and second pairs of bipolar transistors,

wherein said MOS transistor logic means responds to said bipolar logic control signal and establishes a second power source current path therein, instead of said first power source current path, for setting or resetting said bipolar logic.

3. A single chip IC as claimed in claim 2, wherein said MOS transistor logic means includes a plurality of n-channel MOS transistors whose gates receive said bipolar logic control signal.

4. A single chip IC as claimed in claim 2, further comprising a constant current source which is provided in series with both said third pair of bipolar transistors and said MOS transistor logic means.

5. A single chip integrated circuit (IC) comprising:

a logic circuit including, in combination, a bipolar logic and a metal-oxide semiconductor (MOS) logic;

a complementary MOS logic; and

a level translator which interfaces said bipolar logic with said complementary MOS logic,

wherein said bipolar logic takes a form of a pair of set/reset type latches which are arranged in tandem with each other and which each comprises;

first and second pairs of bipolar transistors, provided in parallel between power sources, for respectively receiving and latching data;

a third pair of bipolar transistors, coupled in series, between said power sources, with said first and second pairs of bipolar transistors, said third pair of bipolar transistors responding to a clock signal applied thereto and switching a first power source current path between said first and second pairs of bipolar transistors, and

wherein said MOS logic receives a bipolar logic control signal directly from said complementary MOS logic and establishes a second power source current path therein, instead of said first power source current path, for setting or resetting said bipolar logic.

6. A single chip IC as claimed in claim 5, wherein said MOS transistor logic means includes a plurality of n-channel MOS transistors whose gates receive said bipolar logic control signal.

7. A single chip IC as claimed in claim 5, further comprising a constant current source which is provided in series with both said third pair of bipolar transistors and said MOS transistor logic means.