Asynchronous transfer mode based service consolidation switch

• US 5,850,395 A
• Filed: 07/18/1996
• Issued: 12/15/1998
• Est. Priority Date: 07/19/1995
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited, Fujitsu Network Communications Incorporated (Fujitsu Limited)
• Inventors: Hauser, Stephen A., Caldara, Stephen A., Manning, Thomas A., McClure, Robert B.
• Primary Examiner(s): VU, HUY DUY
• Application Number:
  US08/683,795
• Time in Patent Office: 880 Days
• Field of Search: 370/395, 370/392, 370/396, 370/397, 370/398, 370/399, 370/412, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/419, 370/420, 370/421, 370/425, 370/422, 370/426, 370/466, 370/467, 370/468
• US Class Current: 370/398
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/4608 LAN interconnection over ATM networks
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5628 Testing
• CPC Class Codes: H04L 2012/5629 Admission control
• CPC Class Codes: H04L 2012/5631 Resource management and allocation
• CPC Class Codes: H04L 2012/5632 Bandwidth allocation
• CPC Class Codes: H04L 2012/5634 In-call negotiation
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5642 Multicast/broadcast/point-multipoint, e.g. VOD
• CPC Class Codes: H04L 2012/5643 Concast/multipoint-to-point
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5648 : Packet discarding, e.g. EPD, PTD
• CPC Class Codes: H04L 2012/5649 : Cell delay or jitter
• CPC Class Codes: H04L 2012/565 : Sequence integrity
• CPC Class Codes: H04L 2012/5651 : Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 : Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5672 : Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 2012/5679 : Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 : Buffer or queue management
• CPC Class Codes: H04L 2012/5682 : Threshold; Watermark
• CPC Class Codes: H04L 2012/5683 : for avoiding head of line blocking
• CPC Class Codes: H04L 2012/5684 : Characteristics of traffic flows
• CPC Class Codes: H04L 2012/5685 : Addressing issues
• CPC Class Codes: H04L 41/00 : Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
• CPC Class Codes: H04L 41/0896 : Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities flow or congestion control using dynamic resource allocation, e.g. in-call renegotiation, H04L47/76
• CPC Class Codes: H04L 41/0897 : by horizontal or vertical scaling of resources, or by migrating entities, e.g. virtual resources or entities
• CPC Class Codes: H04L 41/40 : using virtualisation of network functions or resources, e.g. SDN or NFV entities
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 47/11 : Identifying congestion
• CPC Class Codes: H04L 47/15 : in relation to multipoint traffic arrangements for broadcast or multicast in data networks H04L12/18
• CPC Class Codes: H04L 47/16 : in connection oriented networks, e.g. frame relay
• CPC Class Codes: H04L 47/18 : End to end
• CPC Class Codes: H04L 47/26 : using explicit feedback to the source, e.g. choke packets
• CPC Class Codes: H04L 47/266 : Stopping or restarting the source, e.g. X-on or X-off
• CPC Class Codes: H04L 47/29 : using a combination of thresholds
• CPC Class Codes: H04L 47/30 : in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/50 : Queue scheduling
• CPC Class Codes: H04L 47/52 : by attributing bandwidth to queues
• CPC Class Codes: H04L 47/521 : Static queue service slot or fixed bandwidth allocation
• CPC Class Codes: H04L 47/522 : Dynamic queue service slot or variable bandwidth allocation
• CPC Class Codes: H04L 47/525 : by redistribution of residual bandwidth
• CPC Class Codes: H04L 47/56 : implementing delay-aware scheduling
• CPC Class Codes: H04L 47/621 : Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 47/6215 : Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 47/6225 : Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 47/627 : policing
• CPC Class Codes: H04L 47/70 : Admission control; Resource allocation
• CPC Class Codes: H04L 47/722 : at the destination endpoint, e.g. reservation of terminal resources or buffer space
• CPC Class Codes: H04L 47/743 : Reaction at the end points
• CPC Class Codes: H04L 47/745 : Reaction in network
• CPC Class Codes: H04L 47/762 : triggered by the network
• CPC Class Codes: H04L 47/782 : Hierarchical allocation of resources, e.g. involving a hierarchy of local and centralised entities
• CPC Class Codes: H04L 47/805 : QOS or priority aware
• CPC Class Codes: H04L 47/822 : Collecting or measuring resource availability data
• CPC Class Codes: H04L 49/101 : using crossbar or matrix
• CPC Class Codes: H04L 49/103 : using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/106 : using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/107 : using shared medium
• CPC Class Codes: H04L 49/108 : using shared central buffer
• CPC Class Codes: H04L 49/153 : ATM switching fabrics having parallel switch planes
• CPC Class Codes: H04L 49/1553 : Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/1576 : Crossbar or matrix
• CPC Class Codes: H04L 49/20 : Support for services
• CPC Class Codes: H04L 49/201 : Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/203 : ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/205 : Quality of Service based
• CPC Class Codes: H04L 49/25 : Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/253 : using establishment or release of connections between ports
• CPC Class Codes: H04L 49/254 : Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/255 : Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/256 : Routing or path finding in ATM switching fabrics
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/309 : Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/455 : Provisions for supporting expansion in ATM switches
• CPC Class Codes: H04L 49/503 : Policing
• CPC Class Codes: H04L 49/505 : Corrective measures
• CPC Class Codes: H04L 49/506 : Backpressure
• CPC Class Codes: H04L 49/508 : Head of Line Blocking Avoidance
• CPC Class Codes: H04L 49/55 : Prevention, detection or correction of errors
• CPC Class Codes: H04L 49/552 : by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/322 : Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
• CPC Class Codes: H04L 69/324 : in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 7/046 : using a dotting sequence
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections
• CPC Class Codes: H04W 28/14 : using intermediate storage
• CPC Class Codes: Y10S 370/902 : Packet switching
• CPC Class Codes: Y10S 370/905 : Asynchronous transfer mode, ASN

Abstract

An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).

Claims

1. An asynchronous transfer mode based service consolidation switch, comprising:

a first port processor operable to receive network traffic over an input link from a network source in one of plural port processor queues, the first port processor operable to convert the network traffic into internal cells having an internal cell based format;

a bandwidth arbiter operable to determine appropriate bandwidth in order to transfer the internal cells from a first queue of said plural port processor queues, and to assign dedicated bandwidth uniquely available to the first queue and dynamic bandwidth shared by the first queue and other queues of said plural port processor queues;

a data crossbar operable to transfer the internal cells from the first port processor queue in response to bandwidth determined by the bandwidth arbiter;

a second port processor operable to receive the internal cells from the data crossbar, the second port processor operable to convert the internal cells into a network traffic configuration for transfer over an output link; and

a multipoint topology controller operable to control a flow of internal cells within the data crossbar.

2. The switch of claim 1, wherein the bandwidth arbiter is operable to assign dedicated bandwidth not being used by the first port processor queue to any of the plurality of other first port processor queues.

3. The switch of claim 1, wherein the first port processor is operable to provide a transfer request to the multipoint topology controller, the transfer request indicating that internal cells have been generated that are destined for the second port processor.

4. The switch of claim 3, wherein the multipoint topology controller is operable to receive the transfer request from the first port processor, the multipoint topology controller operable to provide a probe inquiry to the second port processor, the probe inquiry being used to determine if the second port processor has resources to accept internal cells from the first port processor.

5. The switch of claim 4, wherein the second port processor is operable to receive the probe inquiry from the multipoint topology controller, the second port processor operable to provide an XON signal to the multipoint topology controller, the XON signal indicating that the second port processor has resources available to receive internal cells from the first port processor.

6. The switch of claim 5, wherein the multipoint topology controller is operable to pass the XON signal to the first port processor, the first port processor operable to transfer the internal cells destined for the second port processor over the data crossbar according to bandwidth allocated by the bandwidth arbiter in response to the XON signal.

7. The switch of claim 4, wherein the second port processor is operable to receive the probe inquiry from the multipoint topology controller, the second port processor operable to provide an XOFF signal to the multipoint topology controller, the XOFF signal indicating that the second port processor does not have the resources to accept internal cells from the first port processor.

8. The switch of claim 7, wherein the multipoint topology controller is operable to pass the XOFF signal to the first port processor, the first port processor operable to hold internal cells destined for the second port processor pending an indication that the second port processor is ready to accept internal cells from the first port processor.

9. The switch of claim 1, further comprising:

an associated second processor paired with the first port processor, the first port processor operable to provide a send signal to the associated second port processor, the send signal indicating that the first port processor has transferred cells over the data crossbar and is ready to accept additional network traffic over the input link.

10. The switch of claim 9, wherein the associated second port processor is operable to send an accept signal to the network source to indicate that the first port processor is ready to receive network traffic over the input link from the network source.

11. An asynchronous transfer mode based service consolidation switch, comprising:

a plurality of input/output modules, each input/output module having a first port processor and associated port processor queues operable to receive traffic from an input link, the first port processor operable to generate internal cells having an internal asynchronous transfer mode cell based format in response to the traffic received over the input link, each input/output module having a second port processor associated with its first port processor, the associated second port processor operable to receive internal cells from other first port processors, the associated second port processor operable to generate traffic for transfer over an output link in response to the internal cells received; and

a switch control module coupled to the plurality of input/output modules, the switch control module having a data crossbar operable to transfer internal cells from an originating first port processor of any of the plurality of input/output modules to a destination second port processor of any of the plurality of input/output modules, the switch control module having a bandwidth arbiter operable to control internal cell transfer between the originating first port processor queue and the destination second port processor according to a quantity of bandwidth of said data crossbar available for said internal cell transfer, the switch control module having a multipoint topology controller associated with each first port processor, the multipoint topology controller operable to schedule transfer of internal cells from the originating first port processor to the destination second port processor;

wherein the bandwidth arbiter is operable to assign dedicated bandwidth to a first queue of the originating first port processor that is not available to other first port processor queues, and operable to assign dynamic bandwidth that is available to two or more of said first port processor queues.

12. The switch of claim 11, wherein the originating first port processor is operable to send a request for data crossbar bandwidth to the bandwidth arbiter in response to generation of internal cells, the bandwidth arbiter operable to accumulate bandwidth requests from first port processors of each of the plurality of input/output modules, the bandwidth arbiter operable to arbitrate all bandwidth requests in allocating bandwidth of the data crossbar.

13. The switch of claim 11, wherein the originating first port processor is operable to send a transfer indication to the multipoint topology controller that an internal cell has been generated and is ready to be transferred, the originating first port processor operable to receive a release signal from the multipoint topology controller, the originating first port processor operable to prepare the internal cell for transfer in response to the release signal.

14. The switch of claim 13, wherein the multipoint topology controller is operable to send a probe inquiry to the destination second port processor in response to the transfer indication from the originating first port processor in order to determine whether the destination second port processor has available buffer space, the multipoint topology controller operable to send the release signal to the originating first port processor in order to initiate cell transfer in response to an indication that the destination second port processor has available buffer space.

15. The switch of claim 14, wherein the destination second port processor is operable to receive the probe inquiry from the multipoint topology controller, the destination second port processor operable to determine whether sufficient resources are available to receive an internal cell from the originating first port processor in response to the probe inquiry.

16. The switch of claim 11, wherein the originating first port processor provides its associated second port processor a send indication of a transfer of internal cells in order to provide link flow control.

17. The switch of claim 16, wherein the associated second port processor is operable to receive the send indication from the originating first port processor, the associated second port processor operable to provide a flow control signal to the network over the output link, the flow control signal indicating that the originating first port processor is ready to accept additional traffic over the input link.

18. The switch of claim 11, wherein the bandwidth arbiter is operable to assign dedicated bandwidth not being used by the first queue of the originating first port processor to the other first port processor queues.