Apparatus and method for recovering a clock signal which is embedded in an incoming data stream

• US 5,850,422 A
• Filed: 07/21/1995
• Issued: 12/15/1998
• Est. Priority Date: 07/21/1995
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Symbios Inc (Broadcom, Inc.)
• Inventors: Chen, Dao-Long
• Primary Examiner(s): Vo, Don N.
• Application Number:
  US08/505,044
• Time in Patent Office: 1,243 Days
• Field of Search: 375/371, 375/373, 375/375, 375/376, 375/327, 370/517, 370/518, 331/1 R, 331/17, 331/57, 331/60, 327/145, 327/147, 327/150, 327/151, 327/152, 327/157, 327/159
• US Class Current: 375/371
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.

Claims

1. A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

providing the incoming data stream to a data sampler circuit;

operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

generating a recovered clock signal based on the selected clock phase;

retiming the incoming data stream based on the recovered clock signal; and

disabling operation of the data sampler circuit immediately after the one of the plurality of clock phases is selected.

2. A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

providing the incoming data stream to a data sampler circuit;

operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

generating a recovered clock signal based on the selected clock phase;

retiming the incoming data stream based on the recovered clock signal; and

disabling operation of the data sampler circuit;

wherein the operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and

wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.

3. A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

providing the incoming data stream and a plurality of clock phases to a data sampler circuit;

first operating the data sampler circuit to select one of the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

generating a recovered clock signal based on the selected clock phase;

second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and

disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode.

4. The method of claim 3, wherein the first operating step includes the step of:

strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase.

5. The method of claim 3, further including the step of:

providing an analog phase-locked loop for generating the plurality of clock phases.

6. A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

providing the incoming data stream to a data sampler circuit;

first operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

generating a recovered clock signal based on the selected clock phase;

second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal; and

disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode;

wherein the first operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase; and

wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.

7. An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;

a clock multiplexer for generating a recovered clock signal based on the selected clock phase;

a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal;

a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer; and

means for disabling said data sampler circuit while said digital phase-locked loop circuit is operating in a normal data tracking mode.

8. An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;

a clock multiplexer for generating a recovered clock signal based on the selected clock phase;

a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and

a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer.

9. The apparatus of claim 8, wherein said loop filter circuit includes a bi-directional shift register loop filter circuit.

10. The apparatus of claim 8, wherein said loop filter circuit includes a up/down counter loop filter circuit.

11. An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;

a clock multiplexer for generating a recovered clock signal based on the selected clock phase;

a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal; and

a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer;

wherein said data sampler circuit includes a feedback circuit for disabling said data sampler circuit in response to selection of the clock phase indicative of the embedded clock signal.

12. An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

means for selecting a clock phase from a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

means for generating a recovered clock signal based on the selected clock phase;

means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and

means for disabling said selecting means while said retiming means is operating in the normal data tracking mode, wherein said disabling means includes a feedback circuit which is coupled to said selecting means and said retiming means.

13. An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

means for generating a plurality of clock phases;

means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

means for generating a recovered clock signal based on the selected clock phase; and

means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode, wherein said retiming means includes a lead/lag phase detector circuit coupled to said selecting means.

14. The apparatus of claim 13, wherein said timing means further includes a bi-directional shift register loop filter circuit coupled to said lead/lag phase detector circuit.

15. An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

means for generating a recovered clock signal based on the selected clock phase;

means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode;

means for disabling said selecting means while said retiming means is operating in the normal data tracking mode; and

a five-stage voltage controlled oscillator for generating the plurality of clock phases, wherein the plurality of clock phases is ten clock phases.

16. An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

means for generating a plurality of clock phases;

means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;

means for generating a recovered clock signal based on the selected clock phase;

means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode; and

means for disabling said selecting means while said retiming means is operating in the normal data tracking